Roberto Giorgi

94 papers A 2C 13Misc 6Journal 28Unranked 38

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Survey on Real-Time Object Detection on FPGAs. IEEE Access Seyed Hani Hozhabr, Roberto Giorgi
2025	—	`ed.`	Applied Reconfigurable Computing. Architectures, Tools, and Applications - 21st International Symposium, ARC 2025, Seville, Spain, April 9-11, 2025, Proceedings ARC Roberto Giorgi, Mirjana Stojilovic, Dirk Stroobandt, Piedad Brox Jiménez, Angel Barriga Barros
2025	—	`conf`	Enhancing Traffic Prediction with Spatio-Temporal Deep Learning: A GCN-LSTM Hybrid Model. MECO Aditi Ghosh, Maurizio Giacobbe, Muhammad Tahir Rafiq, Antonio Puliafito, Roberto Giorgi
2025	J	`jnl`	FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm. CoRR Roberto Giorgi
2025	J	`jnl`	HashGrid: An optimized architecture for accelerating graph computing on FPGAs. Future Gener. Comput. Syst. Amin Sahebi, Marco Procaccini, Roberto Giorgi
2025	—	`conf`	Real-time Object Detection on FPGA-based Heterogeneous MPSoCs: A Preliminary Analysis of the Execution Bottlenecks. MECO Seyed Hani Hozhabr, Roberto Giorgi
2025	J	`jnl`	WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes. CoRR Roberto Giorgi, Gianfranco Mariotti
2024	J	`jnl`	A survey of graph convolutional networks (GCNs) in FPGA-based accelerators. J. Big Data Marco Procaccini, Amin Sahebi, Roberto Giorgi
2024	—	`conf`	Accelerating Large-Scale Graph Processing with FPGAs: Lesson Learned and Future Directions. PARMA-DITAM Marco Procaccini, Amin Sahebi, Marco Barbone, Wayne Luk, Georgi Gaydadjiev, Roberto Giorgi
2024	—	`conf`	DF-Threads: A Scalable and Efficient Execution Paradigm for Edge Computing and HPC. BigHPC@itaDATA Roberto Giorgi
2023	J	`jnl`	Distributed large-scale graph processing on FPGAs. J. Big Data Amin Sahebi, Marco Barbone, Marco Procaccini, Wayne Luk, Georgi Gaydadjiev, Roberto Giorgi
2022	—	`conf`	Extending Performance and Reliability via Modular FPGA Clusters. MECO Roberto Giorgi
2022	J	`jnl`	WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool. SoftwareX Gianfranco Mariotti, Roberto Giorgi
2021	—	`conf`	DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model. ARCS Roberto Giorgi, Marco Procaccini, Amin Sahebi
2021	J	`jnl`	The AXIOM Project: IoT on Heterogeneous Embedded Platforms. IEEE Des. Test Antonio Filgueras, Miquel Vidal, Marc Mateu, Daniel Jiménez-González, Carlos Álvarez, Xavier Martorell, Eduard Ayguadé, Dimitrios Theodoropoulos, Dionisios N. Pnevmatikatos, Paolo Gai, Stefano Garzarella, David Oro, Javier Hernando, Nicola Bettin, Alberto Pomella, Marco Procaccini, Roberto Giorgi
2021	—	`conf`	The Italian research on HPC key technologies across EuroHPC. CF Marco Aldinucci, Giovanni Agosta, Antonio Andreini, Claudio Agostino Ardagna, Andrea Bartolini, Alessandro Cilardo, Biagio Cosenza, Marco Danelutto, Roberto Esposito, William Fornaciari, Roberto Giorgi, Davide Lengani, Raffaele Montella, Mauro Olivieri, Sergio Saponara, Daniele Simoni, Massimo Torquati
2019	—	`conf`	A Data-Flow Methodology for Accelerating FFT. MECO Lorenzo Verdoscia, Amin Sahebi, Roberto Giorgi
2019	—	`conf`	A Design Space Exploration Tool Set for Future 1K-core High-Performance Computers. RAPIDO Roberto Giorgi, Marco Procaccini, Farnam Khalili
2019	A	`conf`	AXIOM: A Scalable, Efficient and Reconfigurable Embedded Platform. DATE Roberto Giorgi, Marco Procaccini, Farnam Khalili
2019	—	`conf`	An Iris+Voice Recognition System for a Smart Doorbell. MECO Roberto Giorgi, Nicola Bettin, Sara Ermini, Francesco Montefoschi, Antonio Rizzo
2019	C	`conf`	Analyzing the Impact of Operating System Activity of Different Linux Distributions in a Distributed Environment. PDP Roberto Giorgi, Marco Procaccini, Farnam Khalili
2019	—	`conf`	Bridging a Data-Flow Execution Model to a Lightweight Programming Model. HPCS Roberto Giorgi, Marco Procaccini
2019	—	`conf`	Embedded Face Analysis for Smart Videosurveillance. MECO Roberto Giorgi, David Oro, Sara Ermini, Francesco Montefoschi, Antonio Rizzo
2019	J	`jnl`	Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise - Designing a Computer Architecture via HLS). Int. J. Reconfigurable Comput. Roberto Giorgi, Farnam Khalili, Marco Procaccini
2019	—	`conf`	WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment. WCAE@ISCA Roberto Giorgi, Gianfranco Mariotti
2018	—	`conf`	Energy Efficiency Exploration on the ZYNQ Ultrascale+. ICM Roberto Giorgi, Farnam Khalili, Marco Procaccini
2018	J	`jnl`	Scalable embedded computing through reconfigurable hardware: Comparing DF-Threads, cilk, openmpi and jump. Microprocess. Microsystems Roberto Giorgi
2017	—	`conf`	AXIOM: A 64-bit reconfigurable hardware/software platform for scalable embedded computing. MECO Roberto Giorgi
2017	—	`conf`	AXIOM: A 64-bit reconfigurable hardware/software platform for scalable embedded computing. MECO Roberto Giorgi
2017	J	`jnl`	Chapter Two - Exploring Future Many-Core Architectures: The TERAFLUX Evaluation Framework. Adv. Comput. Roberto Giorgi
2017	—	`conf`	Rapid prototyping IoT solutions based on Machine Learning. ECCE Antonio Rizzo, Francesco Montefoschi, Maurizio Caporali, Antonio Gisondi, Giovanni Burresi, Roberto Giorgi
2017	J	`jnl`	The AXIOM platform for next-generation cyber physical systems. Microprocess. Microsystems Dimitris Theodoropoulos, Somnath Mazumdar, Eduard Ayguadé, Nicola Bettin, Javier Bueno, Sara Ermini, Antonio Filgueras, Daniel Jiménez-González, Carlos Álvarez-Martínez, Xavier Martorell, Francesco Montefoschi, David Oro, Dionisis N. Pnevmatikatos, Antonio Rizzo, Paolo Gai, Stefano Garzarella, Bruno Morelli, Alberto Pomella, Roberto Giorgi
2016	C	`conf`	AXIOM: A Hardware-Software Platform for Cyber Physical Systems. DSD Somnath Mazumdar, Eduard Ayguadé, Nicola Bettin, Javier Bueno, Sara Ermini, Antonio Filgueras, Daniel Jiménez-González, Carlos Álvarez-Martínez, Xavier Martorell, Francesco Montefoschi, David Oro, Dionisios N. Pnevmatikatos, Antonio Rizzo, Dimitris Theodoropoulos, Roberto Giorgi
2016	J	`jnl`	Architectural Support for Fault Tolerance in a Teradevice Dataflow System. Int. J. Parallel Program. Sebastian Weis, Arne Garbade, Bernhard Fechner, Avi Mendelson, Roberto Giorgi, Theo Ungerer
2016	—	`conf`	Exploring dataflow-based thread level parallelism in cyber-physical systems. Conf. Computing Frontiers Roberto Giorgi
2016	J	`jnl`	Making IoT with UDOO. IxD&A Antonio Rizzo, Giovanni Burresi, Francesco Montefoschi, Maurizio Caporali, Roberto Giorgi
2015	—	`conf`	A field experience for a vehicle recognition system using magnetic sensors. MECO Giovanni Burresi, Roberto Giorgi
2015	—	`conf`	A matrix multiplier case study for an evaluation of a configurable dataflow-machine. Conf. Computing Frontiers Lorenzo Verdoscia, Roberto Vaccaro, Roberto Giorgi
2015	J	`jnl`	A scalable thread scheduling co-processor based on data-flow principles. Future Gener. Comput. Syst. Roberto Giorgi, Alberto Scionti
2015	C	`conf`	Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions. DSD Andrea Mondelli, Nam Ho, Alberto Scionti, Marco Solinas, Antoni Portero, Roberto Giorgi
2015	—	`conf`	Enhancing an x86_64 multi-core architecture with data-flow execution support. Conf. Computing Frontiers Nam Ho, Andrea Mondelli, Alberto Scionti, Marco Solinas, Antoni Portero, Roberto Giorgi
2015	—	`book`	Guide to DataFlow Supercomputing - Basic Concepts, Case Studies, and a Detailed Example Veljko Milutinovic, Jakob Salom, Nemanja Trifunovic, Roberto Giorgi
2015	C	`conf`	Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing. EUC Roberto Giorgi
2015	J	`jnl`	Special Section on Terascale Computing. Future Gener. Comput. Syst. Stefan Wesner, Lutz Schubert, Rosa M. Badia, Antonio Rubio, Pier Stanislao Paolucci, Roberto Giorgi
2015	C	`conf`	The AXIOM Software Layers. DSD Carlos Álvarez, Eduard Ayguadé, Javier Bueno, Antonio Filgueras, Daniel Jiménez-González, Xavier Martorell, Nacho Navarro, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Davide Catani, Claudio Scordino, Paolo Gai, Carlos Segura, Carles Fernández, David Oro, Javier Rodríguez Saeta, Pierluigi Passera, Alberto Pomella, Antonio Rizzo, Roberto Giorgi
2015	—	`conf`	The AXIOM project (Agile, eXtensible, fast I/O Module). SAMOS Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Carlos Álvarez, Eduard Ayguadé, Javier Bueno, Antonio Filgueras, Daniel Jiménez-González, Xavier Martorell, Nacho Navarro, Carlos Segura, Carles Fernández, David Oro, Javier Rodríguez Saeta, Paolo Gai, Antonio Rizzo, Roberto Giorgi
2014	—	`conf`	An Introduction to DF-Threads and their Execution Model. SBAC-PAD (Workshops) Roberto Giorgi, Paolo Faraboschi
2014	—	`conf`	Dynamic power reduction in self-adaptive embedded systems through benchmark analysis. MECO Alberto Scionti, Stamatios Kavvadias, Roberto Giorgi
2014	C	`conf`	Integration of simulators in virtual 3D computer science classroom. EDUCON Irina Branovic, Ranko Popovic, Nenad Jovanovic, Roberto Giorgi, Bosko Nikolic, Miodrag Zivkovic
2014	J	`jnl`	TERAFLUX: Harnessing dataflow in next generation teradevices. Microprocess. Microsystems Roberto Giorgi, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Rahulkumar Gayatri, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Joshua Landwehr, Nhat Minh Lê, Feng Li, Mikel Luján, Avi Mendelson, Laurent Morin, Nacho Navarro, Tomasz Patejko, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Ian Watson, Sebastian Weis, Stéphane Zuckerman, Mateo Valero
2013	C	`conf`	The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices. DSD Marco Solinas, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Feng Li, Mikel Luján, Laurent Morin, Avi Mendelson, Nacho Navarro, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Mateo Valero, Sebastian Weis, Ian Watson, Stéphane Zuckerman, Roberto Giorgi
2012	Misc	`conf`	Embedded reconfigurable architectures. CASES Stephan Wong, Luigi Carro, Stamatios Kavvadias, Georgios Keramidas, Francesco Papariello, Claudio Scordino, Roberto Giorgi, Stefanos Kaxiras
2012	—	`conf`	Simulating the future kilo-x86-64 core processors and their infrastructure. SpringSim (ANSS) Antoni Portero, Alberto Scionti, Zhibin Yu, Paolo Faraboschi, Caroline Concatto, Luigi Carro, Arne Garbade, Sebastian Weis, Theo Ungerer, Roberto Giorgi
2012	—	`conf`	TERAFLUX: exploiting dataflow parallelism in teradevices. Conf. Computing Frontiers Roberto Giorgi
2011	—	`conf`	TERAFLUX: Exploiting Tera-device Computing Challenges. FET Antoni Portero, Zhibin Yu, Roberto Giorgi
2010	C	`conf`	Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed. ISCAS Massimo Alioto, Paolo Bennati, Roberto Giorgi
2009	A	`conf`	Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture. IPDPS Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
2009	—	`conf`	Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture. SAMOS Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
2009	—	`ch.`	Instruction Set Extensions for Cryptographic Applications. Cryptographic Engineering Sandro Bartolini, Roberto Giorgi, Enrico Martinelli
2009	Misc	`conf`	Introducing Hardware TLP Support in the Cell Processor. CISIS Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
2009	—	`ed.`	Proceedings of the 10th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '09, Raleigh, North Carolina, USA, September 13, 2009 MEDEA@PACT Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
2009	C	`conf`	Programming Abstractions and Toolchain for Dataflow Multithreading Architectures. ISPDC Kyriakos Stavrou, Demos Pavlou, Marios Nikolaides, Panayiotis Petrides, Paraskevas Evripidou, Pedro Trancoso, Zdravko Popovic, Roberto Giorgi
2008	C	`conf`	Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. DSD Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Arnaldo Azevedo, Ben H. H. Juurlink
2008	J	`jnl`	Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2 IEEE Trans. Computers Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli
2008	Misc	`conf`	Filtering drowsy instruction cache to achieve better efficiency. SAC Roberto Giorgi, Paolo Bennati
2008	—	`ed.`	Proceedings of the 9th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '08, Toronto, Canada, October 26, 2008 MEDEA@PACT Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi
2008	C	`conf`	Reducing Leakage through Filter Cache. DSD Roberto Giorgi, Paolo Bennati
2007	C	`conf`	DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems. SBAC-PAD Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
2007	—	`ed.`	Proceedings of the 2007 workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '07, Brasov, Romania, September 16, 2007 MEDEA@PACT Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi
2007	—	`conf`	Reducing leakage in power-saving capable caches for embedded systems by using a filter cache. MEDEA@PACT Roberto Giorgi, Paolo Bennati
2006	J	`jnl`	Issues in Embedded Single-Chip Multicore Architectures. J. Embed. Comput. Sandro Bartolini, Roberto Giorgi
2006	J	`jnl`	Memory performance: dealing with applications, systems and architecture. SIGARCH Comput. Archit. News Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
2005	J	`jnl`	Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload. J. Parallel Distributed Comput. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
2004	C	`conf`	A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields. SBAC-PAD Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli
2004	J	`jnl`	A workload characterization of elliptic curve cryptography methods in embedded environments. SIGARCH Comput. Archit. News Irina Branovic, Roberto Giorgi, Enrico Martinelli
2004	—	`ed.`	Proceedings of the 2004 workshop on MEmory performance - DEaling with Applications , systems and architecture, MEDEA '04, Antibes Juan-les-Pins, France, September 29 - October 3, 2004 MEDEA@PACT Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
2004	J	`jnl`	Speeding-up multiprocessors running DBMS workloads through coherence protocols. Int. J. High Perform. Comput. Netw. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
2004	Misc	`conf`	WebMIPS: a new web-based MIPS simulation environment for computer architecture education. WCAE Irina Branovic, Roberto Giorgi, Enrico Martinelli
2002	—	`conf`	Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture. NETWORKING Workshops Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
2002	Misc	`conf`	Web-based training on computer architecture: the case for JCachesim. WCAE Irina Branovic, Roberto Giorgi, Cosimo Antonio Prete
2001	—	`conf`	Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload. HICSS Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
2001	J	`jnl`	Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. SIGARCH Comput. Archit. News Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, Mateo Valero
2001	—	`conf`	Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications. PDCS Krishna M. Kavi, Joseph Arul, Roberto Giorgi
2001	J	`jnl`	Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation. IEEE Trans. Computers Krishna M. Kavi, Roberto Giorgi, Joseph Arul
2000	J	`jnl`	Execution and Cache Performance of the Scheduled Dataflow Architecture. J. Univers. Comput. Sci. Krishna M. Kavi, Joseph Arul, Roberto Giorgi
2000	—	`conf`	Performance Analysis of Electronic Commerce Multiprocessor Server. HICSS Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
1999	J	`jnl`	PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. Roberto Giorgi, Cosimo Antonio Prete
1999	Misc	`conf`	Process Migration Effects on Memory Performance of Multiprocessor. HiPC Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
1998	—	`conf`	An educational environment for designing and performance tuning of embedded systems. WCAE@ISCA Roberto Giorgi, Cosimo Antonio Prete
1998	—	`conf`	Analysis of Sharing Overhead in Shared Memory Multiprocessors. HICSS (7) Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
1997	—	`conf`	A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. HICSS (1) Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi
1997	—	`conf`	Cache memory design for embedded systems based on program locality analysis. MSE Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina
1997	J	`jnl`	Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors. IEEE Concurrency Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi
1996	—	`conf`	A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. EUROMICRO Roberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina