Robert W. Dutton

82 papers A* 4A 6C 1Journal 56Unranked 14
YearRankTypeTitle / Venue / Authors
2011 J jnl
Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology.
Microelectron. Reliab.
Shuqing Cao, Jung-Hoon Chun, Akram A. Salman, Stephen G. Beebe, Robert W. Dutton
2011 J jnl
Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra
2010 J jnl
Circuit-Based Characterization of Device Noise Using Phase Noise Data.
IEEE Trans. Circuits Syst. I Regul. Pap.
Reza Navid, Thomas H. Lee, Robert W. Dutton
2010 J jnl
ESD Design Strategies for High-Speed Digital and RF Circuits in Deeply Scaled Silicon Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shuqing Cao, Jung-Hoon Chun, Stephen G. Beebe, Robert W. Dutton
2010 A conf
Optimized self-tuning for circuit aging.
DATE
Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra
2009 — conf
ESD design challenges and strategies in deeply-scaled integrated circuits.
CICC
Shuqing Cao, Tze Wee Chen, Stephen G. Beebe, Robert W. Dutton
2008 — conf
Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs.
ISQED
Parastoo Nikaeen, Boris Murmann, Robert W. Dutton
2008 — conf
Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices.
ISQED
Jae Wook Kim, Boris Murmann, Robert W. Dutton
2007 J jnl
A Built-in Technique for Measuring Substrate and Power-Supply Digital Switching Noise Using PMOS-Based Differential Sensors and a Waveform Sampler in System-on-Chip Applications.
IEEE Trans. Instrum. Meas.
Cosmin Iorga, Yi-Chang Lu, Robert W. Dutton
2007 C conf
A Circuit-Based Noise Parameter Extraction Technique for MOSFETs.
ISCAS
Reza Navid, Thomas H. Lee, Robert W. Dutton
2007 J jnl
RF ESD protection strategies: Codesign vs. low-C protection.
Microelectron. Reliab.
Wolfgang Soldner, Martin Streibl, U. Hodel, Marc Tiebout, Harald Gossner, Doris Schmitt-Landsiedel, Jung-Hoon Chun, Choshu Ito, Robert W. Dutton
2006 J jnl
Post-breakdown leakage resistance and its dependence on device area.
Microelectron. Reliab.
Tze Wee Chen, Choshu Ito, William Loh, Robert W. Dutton
2006 J jnl
Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs.
IEEE J. Solid State Circuits
Hai Lan, Tze Wee Chen, Chi On Chui, Parastoo Nikaeen, Jae Wook Kim, Robert W. Dutton
2005 J jnl
An analytical formulation of phase noise of signals with Gaussian-distributed jitter.
IEEE Trans. Circuits Syst. II Express Briefs
Reza Navid, Thomas H. Lee, Robert W. Dutton
2005 J jnl
Minimum achievable phase noise of RC oscillators.
IEEE J. Solid State Circuits
Reza Navid, Thomas H. Lee, Robert W. Dutton
2005 — conf
Synthesized compact model and experimental results for substrate noise coupling in lightly doped processes.
CICC
Hai Lan, Tze Wee Chen, Chi On Chui, Parastoo Nikaeen, Jae Wook Kim, Robert W. Dutton
2004 — conf
Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design.
ISQED
Georgios Veronis, Yi-Chang Lu, Robert W. Dutton
2004 A conf
Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs.
DATE
Hai Lan, Robert W. Dutton
2004 J jnl
Virtual-ground sensing techniques for a 49-ns/200-MHz access time 1.8-V 256-Mb 2-bit-per-cell flash memory.
IEEE J. Solid State Circuits
Binh Quang Le, Michael Achter, Chin Ghee Chng, Xin Guo, Lee Cleveland, Pau-Ling Chen, Michael Van Buskirk, Robert W. Dutton
2003 — conf
A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design.
ISQED
Hai Lan, Zhiping Yu, Robert W. Dutton
2003 — conf
Lumped, inductorless oscillators: how far can they go? [phase noise reduction limit].
CICC
Reza Navid, Thomas H. Lee, Robert W. Dutton
2002 J jnl
A noise optimization technique for integrated low-noise amplifiers.
IEEE J. Solid State Circuits
Jung-Suk Goo, Hee-Tae Ahn, Donald J. Ladwig, Zhiping Yu, Thomas H. Lee, Robert W. Dutton
2002 — conf
AC Analysis of Thin Gate Oxide MOS with Quantum Mechanical Corrections.
ISQED
Tae-Young Oh, Zhiping Yu, Robert W. Dutton
2002 — conf
Accurate Model of Metal-Insulator-Semiconductor Interconnects.
ISQED
Gaofeng Wang, Xiaoning Qi, Zhiping Yu, Robert W. Dutton
2002 J jnl
High-frequency characterization of on-chip digital interconnects.
IEEE J. Solid State Circuits
Bendik Kleveland, Xiaoning Qi, Liam Madden, Takeshi Furusawa, Robert W. Dutton, Mark A. Horowitz, S. Simon Wong
2001 A conf
A Software Framework for Creating Patient Specific Geometric Models from Medical Imaging Data for Simulation Based Medical Planning of Vascular Surgery.
MICCAI
Nathan Wilson, Kenneth Wang, Robert W. Dutton, Charles Taylor
2001 — conf
A fast analytical technique for estimating the bounds of on-chip clock wire inductance.
CICC
Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton
2001 — conf
Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications.
ISQED
Choshu Ito, Kaustav Banerjee, Robert W. Dutton
2001 A conf
Will Nanotechnology Change the Way We Design and Verify Systems? (Panel).
ICCAD
Andreas Kuehlmann, Robert W. Dutton, Paul D. Franzon, Seth Copen Goldstein, Philip Luekes, Eric Parker, Thomas N. Theis
2000 — conf
Full Chip Thermal Simulation.
ISQED
Zhiping Yu, Dan Yergeau, Robert W. Dutton, O. Sam Nakagawa, Norman Chang, Shen Lin, Weize Xie
2000 — conf
On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation.
CICC
Xiaoning Qi, Gaofeng Wang, Zhiping Yu, Robert W. Dutton, Tak Young, Norman Chang
2000 J jnl
Perspectives on technology and technology-driven CAD.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Robert W. Dutton, Andrzej J. Strojwas
1999 J jnl
Comprehensive Static Characterization of Vertical Electrostatically Actuated Polysilicon Beams.
IEEE Des. Test Comput.
Edward K. Chan, Krishna Garikipati, Robert W. Dutton
1998 J jnl
Characterization of RF power BJT and improvement of thermal stability with nonlinear base ballasting.
IEEE J. Solid State Circuits
Jaejune Jang, Edwin C. Kan, Torkel Arnborg, Ted Johansson, Robert W. Dutton
1998 J jnl
Hierarchical Process Simulation for Nano-Electronics.
VLSI Design
Robert W. Dutton, Edwin C. Kan
1998 J jnl
Modeling of Poly-Silicon Carrier Transport with Explicit Treatment of Grains and Grain Boundaries.
VLSI Design
Edwin C. Kan, Robert W. Dutton
1998 J jnl
Observation of Anomalous Negative Differential Resistance in Diode Breakdown Simulation Using Carrier Temperature Dependent Impact Ionization.
VLSI Design
Edwin C. Kan, Gyoyoung Jin, Zhiping Yu, Robert W. Dutton
1998 J jnl
Second Order Newton Iteration Method and Its Application to MOS Compact Modeling and Circuit Simulation.
VLSI Design
Zhiping Yu, Robert W. Dutton
1996 J jnl
Simulation of the hydrodynamic device model on distributed memory parallel computers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Narayan R. Aluru, Kincho H. Law, Robert W. Dutton
1995 — conf
A Methodology for Parallelizing PDE Solvers: Application to Semiconductor Device Simulation.
PP
Bruce P. Herndon, Narayan R. Aluru, Arthur Raefsky, Ronald J. G. Goossens, Kincho H. Law, Robert W. Dutton
1995 J jnl
Formulation of Macroscopic Transport Models for Numerical Simulation of Semiconductor Devices.
VLSI Design
Edwin C. Kan, Zhiping Yu, Robert W. Dutton, Datong Chen, Umberto Ravaioli
1995 A conf
Relaxation-based harmonic balance technique for semiconductor device simulation.
ICCAD
Boris Troyanovsky, Zhiping Yu, Lydia So, Robert W. Dutton
1994 J jnl
An automatic biasing scheme for tracing arbitrarily shaped I-V curves.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ronald J. G. Goossens, Stephen G. Beebe, Zhiping Yu, Robert W. Dutton
1993 J jnl
Modeling of the charge balance condition on floating gates and simulation of EEPROMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Datong Chen, Satoshi Sugino, Zhiping Yu, Robert W. Dutton
1993 — book
Technology CAD - computer simulation of IC processes and devices.
Robert W. Dutton, Zhiping Yu
1992 J jnl
A tool towards integration of IC process, device, and circuit simulation.
IEEE J. Solid State Circuits
Goodwin R. Chin, Robert W. Dutton
1992 J jnl
A utility-based integrated system for process simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Edward W. Scheckler, Alexander S. Wong, Robert K. Wang, Goodwin R. Chin, John R. Camagna, Andrew R. Neureuther, Robert W. Dutton
1992 J jnl
An approach to construct pre-conditioning matrices for block iteration of linear equations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ze-Yi Wang, Ke-Chih Wu, Robert W. Dutton
1992 J jnl
Comments, with reply, on 'Metastability of CMOS latch/flip-flop'.
IEEE J. Solid State Circuits
Fred U. Rosenberger, Charles E. Molnar, Robert W. Dutton
1991 J jnl
A STRIDE towards practical 3-D device simulation-numerical and visualization considerations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ke-Chih Wu, Goodwin R. Chin, Robert W. Dutton
1991 A* conf
Linking TCAD to EDA - Benefits and Issues.
DAC
Goodwin R. Chin, Walter C. Dietrich Jr., Duane S. Boning, Alexander S. Wong, Andrew R. Neureuther, Robert W. Dutton
1990 J jnl
'Defensive programming' in the rapid development of a parallel scientific program.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
D. Y. Cheng, J. T. Deutsch, Robert W. Dutton
1990 J jnl
A nonequilibrium one-dimensional quantum-mechanical simulation for AlGaAs/GaAs HEMT structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chiaki Takano, Zhiping Yu, Robert W. Dutton
1990 J jnl
Metastability of CMOS latch/flip-flop.
IEEE J. Solid State Circuits
Lee-Sup Kim, Robert W. Dutton
1989 A conf
A manufacturing-oriented environment for synthesis of fabrication processes.
ICCAD
John S. Wenstrand, Hiroshi Iwai, Robert W. Dutton
1989 J jnl
Improved physical modeling of submicron MOSFETs based on parameter extraction using 2-D simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chang G. Hwang, Robert W. Dutton
1989 J jnl
Improvement in norm-reducing Newton methods for circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hal R. Yeager, Robert W. Dutton
1989 J jnl
Influence of device parameters on the switching speed of BiCMOS buffers.
IEEE J. Solid State Circuits
Geert P. Rosseel, Robert W. Dutton
1989 J jnl
Modeling of the distributed gate RC effect in MOSFET's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lee-Sup Kim, Robert W. Dutton
1989 J jnl
New approaches in a 3-D one-carrier device solver.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ke-Chih Wu, Robert F. Lucas, Ze-Yi Wang, Robert W. Dutton
1989 J jnl
The impact of supercomputing capabilities on U.S. materials science and technology.
Future Gener. Comput. Syst.
William D. Wilson, Robert J. Asaro, Robert W. Dutton, Juan M. Sanchez, David J. Srolovitz, Richard H. Boyd, William A. Goddard III, John R. Smith, Wilhelm G. Wolfer
1989 J jnl
Two-dimensional analysis of a merged BiPMOS device.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
James B. Kuo, Geert P. Rosseel, Robert W. Dutton
1989 J jnl
Two-dimensional transient analysis of a collector-up ECL inverter.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
James B. Kuo, Tsen-Shau Yang, Robert W. Dutton, Bruce A. Wooley
1988 J jnl
Algorithms for optimizing, two-dimensional symbolic layout compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wayne H. Wolf, Robert G. Mathews, John A. Newkirk, Robert W. Dutton
1988 J jnl
Hot carrier transport effect in Schottky-barrier diode grown by MBE.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chang G. Hwang, Robert W. Dutton
1988 J jnl
Methodology for submicron device model development.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vered Marash, Robert W. Dutton
1988 J jnl
PISCES-MC: a multiwindow, multimethod 2-D device simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
D. Y. Cheng, Chang G. Hwang, Robert W. Dutton
1988 J jnl
The efficient simulation of coupled point defect and impurity diffusion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michael R. Kump, Robert W. Dutton
1988 J jnl
Verification of analytic point defect models using SUPREM-IV [dopant diffusion].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark E. Law, Robert W. Dutton
1987 J jnl
An Extension to Newton's Method in Device Simulators--On An Efficient Algorithm to Evaluate Small-Signal Parameters and to Predict Initial Guess.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhiping Yu, Robert W. Dutton, Massimo Vanzi
1987 J jnl
Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor Capacitances.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroshi Iwai, Mark R. Pinto, Conor S. Rafferty, J. E. Oristian, Robert W. Dutton
1986 J jnl
A Best-First Search Algorithm for Optimal PLA Folding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sun Young Hwang, Robert W. Dutton, Tom Blank
1986 J jnl
The use of computer aids in IC technology evolution.
Proc. IEEE
Robert W. Dutton, Mark R. Pinto
1985 J jnl
An Approach to Solving Multiparticle Diffusion Exhibiting Nonlinear Stiff Coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hal R. Yeager, Robert W. Dutton
1985 A* conf
An analytical algorithm for placement of arbitrarily sized rectangular blocks.
DAC
Lu Sha, Robert W. Dutton
1985 J jnl
Iterative Methods in Semiconductor Device Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Conor S. Rafferty, Mark R. Pinto, Robert W. Dutton
1985 J jnl
Lump Partitioning of IC Bipolar Transistor Models for High-Frequency Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
N. N. Chan, Robert W. Dutton
1985 J jnl
Two-Dimensional Numerical Analysis of Latchup in a VLSI CMOS Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Enrico Sangiorgi, Mark R. Pinto, Stanley E. Swirhun, Robert W. Dutton
1983 J jnl
Resistance Extraction from Mask Layout Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark Horowitz, Robert W. Dutton
1982 J jnl
Modeling Latch-Up in CMOS Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Donald B. Estreich, Robert W. Dutton
1981 A* conf
Government interest and involvement in design automation development (Panel Discussion).
DAC
Ronald Waxman, Jonathan Allen, Robert W. Dutton, John M. Gould, Charles W. Gwyn, Paul Losleben, Dan C. Nash, Lawrence Sumney, H. Wayne Spence
1981 A* conf
Position statement - tools for design automation from a university point of view.
DAC
Robert W. Dutton