Robert Najvirt

25 papers A 2C 5Journal 7Unranked 11

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	The Hidden Behavior of a D-Latch. IEEE Trans. Circuits Syst. I Regul. Pap. Jürgen Maier, Andreas Steininger, Robert Najvirt
2023	—	`conf`	ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. ASYNC Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer
2022	C	`conf`	On SAT-Based Model Checking of Speed-Independent Circuits. DDECS Florian Huemer, Robert Najvirt, Andreas Steininger
2021	C	`conf`	An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. DSD Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger
2021	—	`conf`	Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. ASYNC Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger, Zaheer Tabassam
2020	J	`jnl`	A Faithful Binary Circuit Model with Adversarial Noise. CoRR Matthias Függer, Jürgen Maier, Robert Najvirt, Thomas Nowak, Ulrich Schmid
2020	J	`jnl`	A Faithful Binary Circuit Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Matthias Függer, Robert Najvirt, Thomas Nowak, Ulrich Schmid
2020	J	`jnl`	Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? CoRR Andreas Steininger, Robert Najvirt, Jürgen Maier
2020	J	`jnl`	The Metastable Behavior of a Schmitt-Trigger. CoRR Andreas Steininger, Jürgen Maier, Robert Najvirt
2018	A	`conf`	A faithful binary circuit model with adversarial noise. DATE Matthias Függer, Jürgen Maier, Robert Najvirt, Thomas Nowak, Ulrich Schmid
2017	—	`conf`	Measuring Metastability with Free-Running Clocks. ASYNC Robert Najvirt, Thomas Polzer, Andreas Steininger
2016	C	`conf`	Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? DSD Andreas Steininger, Robert Najvirt, Jürgen Maier
2016	J	`jnl`	On the Appropriate Handling of Metastable Voltages in FPGAs. J. Circuits Syst. Comput. Thomas Polzer, Robert Najvirt, Florian Beck, Andreas Steininger
2016	—	`conf`	The Metastable Behavior of a Schmitt-Trigger. ASYNC Andreas Steininger, Jürgen Maier, Robert Najvirt
2015	—	`conf`	A pausible clock with crystal oscillator accuracy. ECCTD Robert Najvirt, Andreas Steininger
2015	—	`conf`	A versatile and reliable glitch filter for clocks. PATMOS Robert Najvirt, Andreas Steininger
2015	C	`conf`	Containment of Metastable Voltages in FPGAs. DDECS Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger
2015	—	`conf`	Experimental Validation of a Faithful Binary Circuit Model. ACM Great Lakes Symposium on VLSI Robert Najvirt, Ulrich Schmid, Michael Hofbauer, Matthias Függer, Thomas Nowak, Kurt Schweiger
2015	—	`conf`	How to Synchronize a Pausible Clock to a Reference. ASYNC Robert Najvirt, Andreas Steininger
2015	A	`conf`	Towards binary circuit models that faithfully capture physical solvability. DATE Matthias Függer, Robert Najvirt, Thomas Nowak, Ulrich Schmid
2014	—	`conf`	Equivalence of clock gating and synchronization with applicability to GALS communication. PATMOS Robert Najvirt, Andreas Steininger
2014	J	`jnl`	Faithful Glitch Propagation in Binary Circuit Models. CoRR Matthias Függer, Robert Najvirt, Thomas Nowak, Ulrich Schmid
2013	C	`conf`	A Multi-Credit Flow Control scheme for asynchronous NoCs. DDECS Syed Rameez Naqvi, Robert Najvirt, Andreas Steininger
2013	—	`conf`	Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. ASYNC Robert Najvirt, Syed Rameez Naqvi, Andreas Steininger
2012	—	`conf`	A Generic Architecture for Robust Asynchronous Communication Links. PATMOS Jakob Lechner, Robert Najvirt