Robert Michael Owens

103 papers A* 10A 3B 1C 8Misc 17Journal 35Unranked 29

Year	Rank	Type	Title / Venue / Authors
2000	J	`jnl`	The design of the MGAP-2: a micro-grained massively parallel array. IEEE Trans. Very Large Scale Integr. Syst. Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
1999	J	`jnl`	A Fast and Simple Steiner Routing Heuristic. Discret. Appl. Math. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
1999	J	`jnl`	Aggressive Dynamic Execution of Decoded Traces. J. VLSI Signal Process. Benjamin Bishop, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
1998	J	`jnl`	A Parallel ASIC Architecture for Efficient Fractal Image Coding. J. VLSI Signal Process. Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens
1998	J	`jnl`	A Very Efficient Storage Structure for DWT and IDWT Filters. J. VLSI Signal Process. Robert Michael Owens, Mohan Vishwanath
1998	—	`conf`	Aggressive Dynamic Execution of Multimedia Kernel Traces. IPPS/SPDP Benjamin Bishop, Robert Michael Owens, Mary Jane Irwin
1998	A*	`conf`	Validation of an Architectural Level Power Analysis Technique. DAC Rita Yu Chen, Robert Michael Owens, Mary Jane Irwin, Raminder Singh Bajwa
1997	—	`conf`	A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines. Great Lakes Symposium on VLSI Eric Gayles, Kevin P. Acken, Robert Michael Owens, Mary Jane Irwin
1997	Misc	`conf`	A Simulation Methodology for Software Energy Evaluation. VLSI Design Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
1997	J	`jnl`	A fast algorithm for minimizing the Elmore delay to identified critical sinks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
1997	A	`conf`	Analysis of power consumption in memory hierarchies. ISLPED Patrick Hicks, Matthew Walnock, Robert Michael Owens
1997	Misc	`conf`	Mixed-autonomy local interconnect for reconfigurable SIMD arrays. HiPC Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
1997	J	`jnl`	Motion Analysis on the Micro Grained Array Processor. Real Time Imaging Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens
1997	J	`jnl`	Power-Area Trade-Offs in Divided Word Line Memory Arrays. J. Circuits Syst. Comput. Meng-Fan Chang, Mary Jane Irwin, Robert Michael Owens
1997	A	`conf`	Techniques for low energy software. ISLPED Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin, Rita Yu Chen, Debashree Ghosh
1997	—	`conf`	The MGAP Family of Processor Arrays. Great Lakes Symposium on VLSI Kevin P. Acken, Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
1996	—	`conf`	A Common Architecture For The DWT and IDWT. ASAP Mohan Vishwanath, Robert Michael Owens
1996	—	`conf`	An Architectural Design For Parallel Fractal Compression. ASAP Kevin P. Acken, Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens
1996	J	`jnl`	An optimal time multiplication free algorithm for edge detection on a mesh. J. VLSI Signal Process. Manjit Borah, Chetana Nagendra, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1996	—	`conf`	Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline. ASAP Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga
1996	J	`jnl`	Architectures for wavelet transforms: A survey. J. VLSI Signal Process. Chaitali Chakrabarti, Mohan Vishwanath, Robert Michael Owens
1996	Misc	`conf`	Design tradeoffs in high speed multipliers and FIR filters. VLSI Design Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
1996	A*	`conf`	Energy Characterization based on Clustering. DAC Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
1996	Misc	`conf`	Instruction level power profiling. ICASSP Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
1996	A	`conf`	Power comparisons for barrel shifters. ISLPED Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens
1996	—	`conf`	Recent Developments in Performance Driven Steiner Routing: An Overview. Great Lakes Symposium on VLSI Manjit Borah, Robert Michael Owens, Mary Jane Irwin
1996	Misc	`conf`	Simultaneous speech segmentation and phoneme recognition using dynamic programming. ICASSP Raminder Singh Bajwa, Robert Michael Owens, Thomas P. Kelliher
1996	—	`conf`	Some Issues in Gray Code Addressing. Great Lakes Symposium on VLSI Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
1996	J	`jnl`	Transistor sizing for low power CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
1995	—	`conf`	A simulation methodology for evaluating parallel computers. SPDP Paul Keltcher, Robert Michael Owens, Mary Jane Irwin
1995	Misc	`conf`	A survey of architectures for the discrete and continuous wavelet transforms. ICASSP Chaitali Chakrabarti, Mohan Vishwanath, Robert Michael Owens
1995	A*	`conf`	Accurate Estimation of Combinational Circuit Activity. DAC Huzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin
1995	J	`jnl`	Digit pipelined arithmetic on fine-grain array processors. J. VLSI Signal Process. Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
1995	—	`conf`	Fast algorithm for performance-oriented Steiner routing. Great Lakes Symposium on VLSI Manjit Borah, Robert Michael Owens, Mary Jane Irwin
1995	—	`conf`	High-throughput and low-power DSP using clocked-CMOS circuitry. ISLPD Manjit Borah, Robert Michael Owens, Mary Jane Irwin
1995	Misc	`conf`	Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering. VLSI Design Manjit Borah, Mary Jane Irwin, Robert Michael Owens
1995	—	`conf`	Motion Estimation Algorithms on Fine Grain Array Processor. ASAP Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens
1995	C	`conf`	Reducing the number of counters needed for integer multiplication. IEEE Symposium on Computer Arithmetic Robert Michael Owens, Raminder Singh Bajwa, Mary Jane Irwin
1995	—	`conf`	The MGAP's programming environment and the *C++ language. ASAP Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
1995	Misc	`conf`	The MGAP-2: an advanced, massively parallel VLSI signal processor. ICASSP Thomas P. Kelliher, Eric Gayles, Robert Michael Owens, Mary Jane Irwin
1995	—	`conf`	Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint. ISLPD Manjit Borah, Robert Michael Owens, Mary Jane Irwin
1995	—	`conf`	Unifying carry-sum and signed-digital number representations for low power. ISLPD Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
1994	J	`jnl`	An edge-based heuristic for Steiner routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Manjit Borah, Robert Michael Owens, Mary Jane Irwin
1994	J	`jnl`	Area Time Trade-Offs in Micro-Grain VLSI Array Architectures. IEEE Trans. Computers Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
1994	—	`conf`	Digit pipelined discrete wavelet transform. ICASSP (2) Chetana Nagendra, Mary Jane Irwin, Robert Michael Owens
1994	—	`conf`	Dynamic Space Warping Algorithms on Fine-Graln Array Processors. IPPS Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens, Chen-Mi Wu
1994	—	`conf`	FPGA-based synthesis of FSMs through decomposition. Great Lakes Symposium on VLSI Wen-Lin Yang, Robert Michael Owens, Mary Jane Irwin
1994	J	`jnl`	Logic synthesis for field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang
1994	J	`jnl`	Polynomial Time Testability of Circuits Generated by Input Decomposition. IEEE Trans. Computers Gueesang Lee, Mary Jane Irwin, Robert Michael Owens
1994	J	`jnl`	Power-delay characteristics of CMOS adders. IEEE Trans. Very Large Scale Integr. Syst. Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
1994	—	`conf`	The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS. HICSS (1) Manjit Borah, Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
1993	Misc	`conf`	A Massively Parallel, Micro-Grained VLSI Architecture. VLSI Design Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
1993	—	`conf`	A new blocked IIR algorithm. ICASSP (3) Chen-Mi Wu, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1993	—	`conf`	Digit systolic algorithms for fine-grain architectures. ASAP Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
1993	—	`conf`	Edge detection using fine-grained parallelism in VLSI. ICASSP (1) Chetana Nagendra, Manjit Borah, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1993	—	`conf`	Image Processing with the MGAP: A Cost Effective Solution. IPPS Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
1993	—	`conf`	Multi-way FSM decomposition based on interconnect complexity. EURO-DAC Wen-Lin Yang, Robert Michael Owens, Mary Jane Irwin
1993	J	`jnl`	The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. IEEE Trans. Very Large Scale Integr. Syst. Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, Wen-Lin Yang
1992	Misc	`conf`	A micro-grained VLSI signal processor. ICASSP Mary Jane Irwin, Robert Michael Owens
1992	Misc	`conf`	An AT ICASSP Mohan Vishwanath, Robert Michael Owens
1992	—	`conf`	Discrete wavelet transforms in VLSI. ASAP Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1992	Misc	`conf`	ECube: An Efficient Architecture for Analyzing Time-Varying Spectra. VLSI Design Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1992	J	`jnl`	ELM-A Fast Addition Algorithm Discovered by a Program. IEEE Trans. Computers Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang
1992	J	`jnl`	Efficiently computing communication complexity for multilevel logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
1992	A*	`conf`	Experiments with a Performance Driven Module Generator. DAC Soohong Kim, Robert Michael Owens, Mary Jane Irwin
1992	—	`conf`	Implementing a family of high performance, micrograined architectures. ASAP Robert Michael Owens, Mary Jane Irwin, Thomas P. Kelliher, Mohan Vishwanath, Raminder Singh Bajwa
1992	—	`conf`	PERFLEX: a performance driven module generator. EURO-DAC Soohong Kim, Robert Michael Owens, Mary Jane Irwin
1991	J	`jnl`	A Two-Dimensional, Distributed Logic Architecture. IEEE Trans. Computers Mary Jane Irwin, Robert Michael Owens
1991	J	`jnl`	Digit Serial Multipliers. J. Parallel Distributed Comput. Poras T. Balsara, Robert Michael Owens, Mary Jane Irwin
1991	—	`conf`	The Arithmetic Cube: error analysis and simulation. ASAP Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
1991	Misc	`conf`	The arithmetic cube II: a second generation VLSI DSP processor. ICASSP Mary Jane Irwin, Robert Michael Owens, Thomas P. Kelliher, Kin-Ki Leung, Mohan Vishwanath
1990	J	`jnl`	A case for digit serial VLSI signal processors. J. VLSI Signal Process. Mary Jane Irwin, Robert Michael Owens
1990	Misc	`conf`	A two-dimensional, distributed logic processor for machine vision. ICASSP Mary Jane Irwin, Robert Michael Owens
1990	C	`conf`	An integrated, multi-level synthesis system. RSP Barry M. Pangrle, Pao-Po Hou, Robert Michael Owens, Mary Jane Irwin
1990	J	`jnl`	Being Stingy with Multipliers. IEEE Trans. Computers Robert Michael Owens, Mary Jane Irwin
1990	Misc	`conf`	Distortion processing in image matching problems. ICASSP Chen-Mi Wu, Robert Michael Owens, Mary Jane Irwin
1990	J	`jnl`	Exploiting communication complexity for multilevel logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
1990	C	`conf`	Logic synthesis for programmable logic devices. ICCD TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
1990	—	`conf`	Mapping high-dimension wavefront computations to silicon. ASAP Chen-Mie Wu, Robert Michael Owens, Mary Jane Irwin
1990	C	`conf`	Test generation in circuits constructed by input decomposition. ICCD Gueesang Lee, Mary Jane Irwin, Robert Michael Owens
1989	A*	`conf`	A Comparison of Four Two-dimensional Gate Matrix Layout Tools. DAC Mary Jane Irwin, Robert Michael Owens
1989	Misc	`conf`	Implementing algorithms for convolution on arrays of adders. ICASSP Robert Michael Owens, Mary Jane Irwin
1989	A*	`conf`	Multi-Level Logic Synthesis Using Communication Complexity. DAC TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
1988	C	`conf`	A comparison of two digit serial VLSI adders. ICCD Mary Jane Irwin, Robert Michael Owens
1988	A*	`conf`	DECOMPOSER: A Synthesizer for Systolic Systems. DAC Pao-Po Hou, Robert Michael Owens, Mary Jane Irwin
1988	Misc	`conf`	Multidimensional algorithms for VLSI processors. ICASSP Robert Michael Owens, Mary Jane Irwin
1987	A*	`conf`	An Overview of the Penn State Design System. DAC Robert Michael Owens, Mary Jane Irwin
1987	J	`jnl`	Digit pipelined processors. J. Supercomput. Mary Jane Irwin, Robert Michael Owens
1987	J	`jnl`	Digit-Pipelined Arithmetic as Illustrated By the Paste-Up System: A Tutorial. Computer Mary Jane Irwin, Robert Michael Owens
1987	A*	`conf`	Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation. DAC Jared A. Beekman, Robert Michael Owens, Mary Jane Irwin
1987	C	`conf`	Systolic & semi-systolic digit serial multipliers. IEEE Symposium on Computer Arithmetic Poras T. Balsara, Robert Michael Owens
1987	J	`jnl`	The Arithmetic Cube. IEEE Trans. Computers Robert Michael Owens, Mary Jane Irwin
1986	J	`jnl`	A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert Michael Owens, Mary Jane Irwin
1986	J	`jnl`	A VLSI chip for the winograd/Prime factor algorithm to compute the discrete Fourier transform. IEEE Trans. Acoust. Speech Signal Process. Robert Michael Owens, Joseph F. JáJá
1986	B	`conf`	Optimal Algorithms for Mesh-Connected Parallel Processors with Serial Memories. ICPP Robert Michael Owens, Joseph F. JáJá
1985	J	`jnl`	Parallel Sorting with Serial Momories. IEEE Trans. Computers Robert Michael Owens, Joseph F. JáJá
1984	J	`jnl`	VLSI Sorting with Reduced Hardware. IEEE Trans. Computers Joseph F. JáJá, Robert Michael Owens
1983	J	`jnl`	An architecture for a VLSI FFT processor. Integr. Joseph F. JáJá, Robert Michael Owens
1983	J	`jnl`	Fully Digit On-Line Networks. IEEE Trans. Computers Mary Jane Irwin, Robert Michael Owens
1983	C	`conf`	Numerical limitations on the design of digit online networks. IEEE Symposium on Computer Arithmetic Robert Michael Owens, Mary Jane Irwin
1983	J	`jnl`	Techniques to Reduce the Inherent Limitations of Fully Digit On-Line Arithmetic. IEEE Trans. Computers Robert Michael Owens
1981	C	`conf`	Compound algorithms for digit online arithmetic. IEEE Symposium on Computer Arithmetic Robert Michael Owens
1979	A*	`conf`	On-Line Algorithms for the Design of Pipeline Architectures. ISCA Robert Michael Owens, Mary Jane Irwin