Robert M. Senger

22 papers A* 1A 7C 3Misc 1Journal 4Unranked 6
YearRankTypeTitle / Venue / Authors
2026 — conf
Spyre: An Inference-Optimized Scalable AI Accelerator for Enterprise Workloads.
ISSCC
Matthew Cohen, Monodeep Kar, Swagath Venkataramani, Viji Srinivasan, Brian Veraa, Matthew M. Ziegler, Nianzheng Cao, Ashish Ranjan, Joel Silberman, Michael Guillorn, Sandra Woodward, JohnDavid Lancaster, Josh Hursey, Kyu-Hyoun Kim, Alberto Mannari, Amrit Nagarajan, Ananda Samajdar, Bahman Hekmatshoartabari, Bob Galbraith, Ching Zhou, David L. Satterfield, Gregory S. Still, Gustavo Tellez, Indira Nair, Indu Masilamanai, Jinwook Jung, Kavi Randhawa, Marcel Schaal, Martin Lutz, Paul Crumley, Philip Jacob, Prasanth Chatarasi, Radhika Jain, Sae Kyu Lee, Sanchari Sen, Sarada Krithivasan, Scot Rider, Shubham Jain, Siyu Koswatta, Thomas Roewer, Tom Gooding, Victor Ferrari, Vidhi Zalani, Zhibin Ren, Kevin Reick, Lisa Maurice, Christopher J. Gonzalez, Chris Catalino, Ryan Nett, Pong-Fei Lu, Robert M. Senger, Leland Chang
2025 J jnl
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC.
IEEE J. Solid State Circuits
Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Röwer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang
2024 — conf
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.
ISSCC
Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang
2023 J jnl
Data Movement Accelerator Engines on a Prototype Power10 Processor.
IEEE Micro
Yutaka Sugawara, Dong Chen, Ruud A. Haring, Abdullah Kayi, Eugene Ratzlaff, Robert M. Senger, Krishnan Sugavanam, Ralph Bellofatto, Ben J. Nathanson, Craig B. Stunkel
2014 — conf
Soft Error Resiliency Characterization on IBM BlueGene/Q Processor.
ASP-DAC
Chen-Yong Cher, K. Paul Muller, Ruud A. Haring, David L. Satterfield, Thomas E. Musta, Thomas Gooding, Kristan D. Davis, Marc Boris Dombrowa, Gerard V. Kopcsay, Robert M. Senger, Yutaka Sugawara, Krishnan Sugavanam
2014 A conf
Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation.
ITC
Chen-Yong Cher, K. Paul Muller, Ruud A. Haring, David L. Satterfield, Thomas E. Musta, Thomas Gooding, Kristan D. Davis, Marc Boris Dombrowa, Gerard V. Kopcsay, Robert M. Senger, Yutaka Sugawara, Krishnan Sugavanam
2013 A conf
Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor.
ISLPED
Alan J. Drake, Michael S. Floyd, Richard L. Willaman, Derek J. Hathaway, Joshua Hernandez, Crystal Soja, Marshall D. Tiner, Gary D. Carpenter, Robert M. Senger
2012 A conf
Looking under the hood of the IBM blue gene/Q network.
SC
Dong Chen, Noel Eisley, Philip Heidelberger, Sameer Kumar, Amith R. Mamidala, Fabrizio Petrini, Robert M. Senger, Yutaka Sugawara, Robert Walkup, Burkhard D. Steinmacher-Burow, Anamitra R. Choudhury, Yogish Sabharwal, Swati Singhal, Jeffrey J. Parker
2012 J jnl
The IBM Blue Gene/Q Interconnection Fabric.
IEEE Micro
Dong Chen, Noel Eisley, Philip Heidelberger, Robert M. Senger, Yutaka Sugawara, Sameer Kumar, Valentina Salapura, David L. Satterfield, Burkhard D. Steinmacher-Burow, Jeffrey J. Parker
2011 A conf
The IBM Blue Gene/Q interconnection network and message unit.
SC
Dong Chen, Noel Eisley, Philip Heidelberger, Robert M. Senger, Yutaka Sugawara, Sameer Kumar, Valentina Salapura, David L. Satterfield, Burkhard D. Steinmacher-Burow, Jeffrey J. Parker
2007 — conf
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor.
ISSCC
Alan J. Drake, Robert M. Senger, Harmander Deogun, Gary D. Carpenter, Soraya Ghiasi, Tuyet Nguyen, Norman K. James, Michael S. Floyd, Vikas Pokala
2006 — conf
A 16-bit, low-power microsystem with monolithic MEMS-
ASP-DAC
Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Richard B. Brown
2006 A conf
A dual-V
ISLPED
Harmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
2006 C conf
DSP architecture for cochlear implants.
ISCAS
Eric D. Marsman, Robert M. Senger, Gordy A. Carichner, Sundus Kubba, Michael S. McCorquodale, Richard B. Brown
2006 C conf
Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking.
ISCAS
Robert M. Senger, Eric D. Marsman, Gordy A. Carichner, Sundus Kubba, Michael S. McCorquodale, Richard B. Brown
2005 — conf
A 16-bit low-power microcontroller with monolithic MEMS-LC clocking.
ISCAS (1)
Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale
2005 A conf
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache.
CGO
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh S. Dasika, Eric D. Marsman, Robert M. Senger, Scott A. Mahlke, Richard B. Brown
2005 J jnl
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.
IEEE Trans. Computers
Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
2003 A* conf
A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference.
DAC
Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown
2003 A conf
A Top-Down Microsystems Design Methodology and Associated Challenges .
DATE
Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, Richard B. Brown
2003 Misc conf
Increasing the number of effective registers in a low-power processor using a windowed register file.
CASES
Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
2003 C conf
Microsystem and SoC Design with UMIPS.
VLSI-SOC
Michael S. McCorquodale, Eric D. Marsman, Robert M. Senger, Fadi H. Gebara, Richard B. Brown