Robert L. Franch

17 papers A 3Journal 11Unranked 3
YearRankTypeTitle / Venue / Authors
2022 — conf
Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning.
ISPD
Matthew M. Ziegler, Lakshmi N. Reddy, Robert L. Franch
2014 — conf
POWER8 design methodology innovations for improving productivity and reducing power.
CICC
Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban
2012 — conf
A shorted global clock design for multi-GHz 3D stacked chips.
VLSIC
Liang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier
2008 A conf
On-chip Timing Uncertainty Measurements on IBM Microprocessors.
ITC
Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem
2007 A conf
On-chip timing uncertainty measurements on IBM microprocessors.
ITC
Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem
2003 J jnl
Estimating the efficiency of collaborative problem-solving, with applications to chip design.
IBM J. Res. Dev.
Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Giovanni Fiorenza, I. Cevdet Noyan
2003 J jnl
The physical design of on-chip interconnections.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan
1997 J jnl
A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file.
IEEE J. Solid State Circuits
Robert L. Franch, J. Ji, C. L. Chen
1992 J jnl
A large V
IEEE J. Solid State Circuits
Robert L. Franch, Sang H. Dhong, Roy E. Scheuerlein
1992 A conf
Advances in Membrane Probe Technology.
ITC
January Kister, Robert L. Franch
1992 J jnl
Measurement of VLSI power supply current by electron-beam probing.
IEEE J. Solid State Circuits
Keith A. Jenkins, Robert L. Franch
1992 J jnl
On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM.
IEEE J. Solid State Circuits
Stanley E. Schuster, Terry I. Chappell, Barbara A. Chappell, Robert L. Franch
1991 J jnl
A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture.
IEEE J. Solid State Circuits
Terry I. Chappell, Barbara A. Chappell, Stanley E. Schuster, James W. Allan, Stephen P. Klepner, Rajiv V. Joshi, Robert L. Franch
1991 J jnl
A 4-Mb low-temperature DRAM.
IEEE J. Solid State Circuits
Walter H. Henkels, Duen-Shun Wen, Rick L. Mohler, Robert L. Franch, Thomas J. Bucelot, Christopher W. Long, John A. Bracchitta, W. J. Cote, Gary B. Bronner, Yuan Taur, Robert H. Dennard
1989 J jnl
A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing.
IEEE J. Solid State Circuits
Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano
1989 J jnl
A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces.
IEEE J. Solid State Circuits
Terry I. Chappell, Stanley E. Schuster, Barbara A. Chappell, James W. Allan, Jack Y.-C. Sun, Stephen P. Klepner, Robert L. Franch, Paul F. Greier, Phillip J. Restle
1988 J jnl
Fast CMOS ECL receivers with 100-mV worst-case sensitivity.
IEEE J. Solid State Circuits
Barbara A. Chappell, Terry I. Chappell, Stanley E. Schuster, Hermann M. Segmuller, James W. Allan, Robert L. Franch, Phillip J. Restle