Robert K. Brayton

319 papers A* 71A 97B 14C 26Misc 6Journal 66Unranked 35

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Enhancing Delay-Driven LUT Mapping With Boolean Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alessandro Tempia Calvino, Giovanni De Micheli, Alan Mishchenko, Robert K. Brayton
2024	J	`jnl`	Practical Boolean Decomposition for Delay-driven LUT Mapping. CoRR Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli, Robert K. Brayton
2022	J	`jnl`	A Simulation-Guided Paradigm for Logic Synthesis and Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
2021	A*	`conf`	Deep Integration of Circuit Simulator and SAT Solver. DAC He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton
2020	J	`jnl`	Simulation-Guided Boolean Resubstitution. CoRR Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
2019	J	`jnl`	Verification and Synthesis of Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Yun Dai, Robert K. Brayton
2018	A*	`conf`	Canonical computation without canonical representation. DAC Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic
2018	A*	`conf`	Efficient computation of ECO patch functions. DAC Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton
2018	—	`ch.`	Identifying Transparent Logic in Gate-Level Circuits. Advanced Logic Synthesis Yu-Yun Dai, Robert K. Brayton
2018	A	`conf`	Improvements to boolean resynthesis. DATE Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli
2018	A	`conf`	Practical exact synthesis. DATE Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli
2018	—	`conf`	SAT-based area recovery in structural technology mapping. ASP-DAC Bruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton
2017	—	`conf`	Circuit recognition with deep learning. HOST Yu-Yun Dai, Robert K. Brayton
2017	A	`conf`	Enabling exact delay synthesis. ICCAD Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli
2017	—	`conf`	Fast-extract with cube hashing. ASP-DAC Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, André Inácio Reis
2017	B	`conf`	Property directed reachability with word-level abstraction. FMCAD Yen-Sheng Ho, Alan Mishchenko, Robert K. Brayton
2016	A	`conf`	2QBF: Challenges and Solutions. SAT Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton
2016	B	`conf`	Efficient uninterpreted function abstraction and refinement for word-level model checking. FMCAD Yen-Sheng Ho, Pankaj Chauhan, Pritam Roy, Alan Mishchenko, Robert K. Brayton
2016	A	`conf`	Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne
2016	A	`conf`	Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli
2016	J	`jnl`	m-Inductive Property of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hamid Savoj, Alan Mishchenko, Robert K. Brayton
2015	—	`conf`	Automated Synthesis of Protocol Converters with BALM-II. SEFM Workshops Giovanni Castagnetti, Matteo Piccolo, Tiziano Villa, Nina Yevtushenko, Robert K. Brayton, Alan Mishchenko
2015	C	`conf`	Bi-Decomposition Using Boolean Relations. DSD Anna Bernasconi, Robert K. Brayton, Valentina Ciriani, Gabriella Trucco, Tiziano Villa
2015	J	`jnl`	Component-Based Design by Solving Language Equations. Proc. IEEE Tiziano Villa, Alexandre Petrenko, Nina Yevtushenko, Alan Mishchenko, Robert K. Brayton
2015	J	`jnl`	Design Automation of Electronic Systems: Past Accomplishments and Challenges Ahead [Scanning the Issue]. Proc. IEEE Robert K. Brayton, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa
2015	A*	`conf`	Sequential equivalence checking of clock-gated circuits. DAC Yu-Yun Dai, Kei-Yong Khoo, Robert K. Brayton
2015	B	`conf`	Simulation Graphs for Reverse Engineering. FMCAD Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton
2015	A	`conf`	Technology Mapping into General Programmable Cells. FPGA Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene
2014	—	`conf`	ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. ASP-DAC Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
2014	—	`conf`	NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract). BCB Aadithya V. Karthik, David Soloveichik, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
2014	J	`jnl`	Sequential Equivalence Checking for Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hamid Savoj, Alan Mishchenko, Robert K. Brayton
2013	A	`conf`	A semi-canonical form for sequential AIGs. DATE Alan Mishchenko, Niklas Eén, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma
2013	A	`conf`	GLA: gate-level abstraction revisited. DATE Alan Mishchenko, Niklas Eén, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla
2013	—	`conf`	LEC: Learning Driven Data-path Equivalence Checking. DIFTS@FMCAD Jiang Long, Robert K. Brayton, Michael L. Case
2013	C	`conf`	Ranking structure in communication fabrics. MEMOCODE Sayak Ray, Robert K. Brayton
2012	A	`conf`	Mapping into LUT structures. DATE Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen
2012	A	`conf`	Scalable progress verification in credit-based flow-control systems. DATE Sayak Ray, Robert K. Brayton
2011	J	`jnl`	Automating Logic Transformations With Approximate SPFDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton
2011	A	`conf`	Delay optimization using SOP balancing. ICCAD Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets
2011	B	`conf`	Efficient implementation of property directed reachability. FMCAD Niklas Eén, Alan Mishchenko, Robert K. Brayton
2011	—	`conf`	Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. DIFTS@FMCAD Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton
2011	J	`jnl`	Scalable don't-care-based logic optimization and resynthesis. ACM Trans. Reconfigurable Technol. Syst. Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang
2010	A*	`conf`	ABC: An Academic Industrial-Strength Verification Tool. CAV Robert K. Brayton, Alan Mishchenko
2010	B	`conf`	Combinational techniques for sequential equivalence checking. FMCAD Hamid Savoj, David Berthelot, Alan Mishchenko, Robert K. Brayton
2010	A	`conf`	Global delay optimization using structural choices. FPGA Alan Mishchenko, Robert K. Brayton, Stephen Jang
2010	J	`jnl`	NSF Workshop on EDA: Past, Present, and Future (Part 1). IEEE Des. Test Comput. Robert K. Brayton, Jason Cong
2010	J	`jnl`	NSF Workshop on EDA: Past, Present, and Future (Part 2). IEEE Des. Test Comput. Robert K. Brayton, Jason Cong
2010	—	`ch.`	Synthesis of Multilevel Boolean Networks. Boolean Models and Methods Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Yves Crama, Peter L. Hammer
2009	A	`conf`	Scalable don't-care-based logic optimization and resynthesis. FPGA Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang
2009	A	`conf`	Sequential logic rectifications with approximate SPFDs. DATE Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith
2009	A	`conf`	SmartOpt: an industrial strength framework for logic synthesis. FPGA Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton
2009	A	`conf`	Speculative reduction-based scalable redundancy identification. DATE Hari Mony, Jason Baumgartner, Alan Mishchenko, Robert K. Brayton
2008	A	`conf`	Boolean factoring and decomposition of logic networks. ICCAD Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee
2008	J	`jnl`	Compositionally Progressive Solutions of Synchronous FSM Equations. Discret. Event Dyn. Syst. Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli
2008	B	`conf`	Invariant-Strengthened Elimination of Dependent State Elements. FMCAD Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony
2008	A*	`conf`	Merging nodes under sequential observability. DAC Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton
2008	A	`conf`	Placement based multiplier rewiring for cell-based designs. ICCAD Fan Mo, Robert K. Brayton
2008	B	`conf`	Recording Synthesis History for Sequential Verification. FMCAD Alan Mishchenko, Robert K. Brayton
2008	A	`conf`	Scalable and scalably-verifiable sequential synthesis. ICCAD Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang
2008	A*	`conf`	Scalable min-register retiming under timing and initializability constraints. DAC Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton
2007	—	`conf`	A new algorithm for the largest compositionally progressive solution of synchronous language equations. ACM Great Lakes Symposium on VLSI Tiziano Villa, Svetlana Zharikova, Nina Yevtushenko, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2007	A	`conf`	A simultaneous bus orientation and bused pin flipping algorithm. ICCAD Fan Mo, Robert K. Brayton
2007	B	`conf`	Automated Extraction of Inductive Invariants to Aid Model Checking. FMCAD Michael L. Case, Alan Mishchenko, Robert K. Brayton
2007	—	`conf`	Automating Logic Rectification by Approximate SPFDs. ASP-DAC Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton
2007	A	`conf`	Combinational and sequential mapping with priority cuts. ICCAD Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton
2007	J	`jnl`	Efficient Solution of Language Equations Using Partitioned Representations CoRR Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
2007	B	`conf`	Fast Minimum-Register Retiming via Binary Maximum-Flow. FMCAD Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton
2007	J	`jnl`	Improvements to Technology Mapping for LUT-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
2007	A*	`conf`	On Resolution Proofs for Combinational Equivalence. DAC Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann
2007	J	`jnl`	SAT-Based Complete Don't-Care Computation for Network Optimization CoRR Alan Mishchenko, Robert K. Brayton
2007	—	`conf`	Semi-detailed bus routing with variation reduction. ISPD Fan Mo, Robert K. Brayton
2006	J	`jnl`	A theory of nondeterministic networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alan Mishchenko, Robert K. Brayton
2006	A*	`conf`	DAG-aware AIG rewriting a fresh look at combinational logic synthesis. DAC Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
2006	A	`conf`	Factor cuts. ICCAD Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton
2006	A	`conf`	Improvements to combinational equivalence checking. ICCAD Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén
2006	A	`conf`	Improvements to technology mapping for LUT-based FPGAs. FPGA Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
2006	J	`jnl`	Reducing Structural Bias in Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam
2006	J	`jnl`	Retiming and Resynthesis: A Complexity Perspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jie-Hong Roland Jiang, Robert K. Brayton
2006	A*	`conf`	Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. DAC Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
2006	J	`jnl`	Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
2005	A	`conf`	Efficient Solution of Language Equations Using Partitioned Representations. DATE Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
2005	—	`conf`	Gaining Predictability and Noise Immunity in Global Interconnects. ACSD Yinghua Li, Alex Kondratyev, Robert K. Brayton
2005	A	`conf`	Reducing structural bias in technology mapping. ICCAD Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam
2005	A	`conf`	SAT-Based Complete Don't-Care Computation for Network Optimization. DATE Alan Mishchenko, Robert K. Brayton
2005	A	`conf`	Synthesis methodology for built-in at-speed testing. ICCAD Yinghua Li, Alex Kondratyev, Robert K. Brayton
2004	A	`conf`	A new incremental placement algorithm and its application to congestion-aware divisor extraction. ICCAD Satrajit Chatterjee, Robert K. Brayton
2004	A*	`conf`	A timing-driven module-based chip design flow. DAC Fan Mo, Robert K. Brayton
2004	A*	`conf`	Functional Dependency for Verification Reduction. CAV Jie-Hong Roland Jiang, Robert K. Brayton
2004	A	`conf`	On breakable cyclic definitions. ICCAD Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
2004	J	`jnl`	SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2003	A	`conf`	A Theory of Non-Deterministic Networks. ICCAD Alan Mishchenko, Robert K. Brayton
2003	—	`conf`	Don't cares in logic minimization of extended finite state machines. ASP-DAC Yunjian Jiang, Robert K. Brayton
2003	A	`conf`	Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. DATE Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli
2003	—	`conf`	Fishbone: a block-level placement and routing scheme. ISPD Fan Mo, Robert K. Brayton
2003	A*	`conf`	Generalized cofactoring for logic function evaluation. DAC Yunjian Jiang, Slobodan Matic, Robert K. Brayton
2003	J	`jnl`	On the verification of sequential equivalence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jie-Hong Roland Jiang, Robert K. Brayton
2003	J	`jnl`	PLA-based regular structures and their synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fan Mo, Robert K. Brayton
2003	A	`conf`	Reducing Multi-Valued Algebraic Operations to Binary. DATE Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
2003	J	`jnl`	Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton
2002	—	`conf`	A Boolean Paradigm in Multi-Valued Logic Synthesis. IWLS Alan Mishchenko, Robert K. Brayton
2002	—	`conf`	Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic. IWLS Yunjian Jiang, Robert K. Brayton
2002	—	`conf`	Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. IWLS Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli
2002	J	`jnl`	Formula-Dependent Equivalence for Compositional CTL Model Checking. Formal Methods Syst. Des. Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2002	—	`conf`	HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. CODES Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2002	—	`conf`	On the Verification of Sequential Equivalence. IWLS Jie-Hong Roland Jiang, Robert K. Brayton
2002	—	`conf`	Optimization of Multi-Valued Multi-Level Networks. ISMVL Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa
2002	—	`conf`	Reducing Multi-Valued Algebraic Operations to Binary. IWLS Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
2002	—	`conf`	Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design. IWLS Fan Mo, Robert K. Brayton
2002	A*	`conf`	River PLAs: a regular circuit structure. DAC Fan Mo, Robert K. Brayton
2002	—	`conf`	Simplification of Non-Deterministic Multi-Valued Networks. IWLS Alan Mishchenko, Robert K. Brayton
2002	A	`conf`	Simplification of non-deterministic multi-valued networks. ICCAD Alan Mishchenko, Robert K. Brayton
2002	A*	`conf`	Software synthesis from synchronous specifications using logic simulation techniques. DAC Yunjian Jiang, Robert K. Brayton
2002	—	`conf`	Topologically Constrained Logic Synthesis. IWLS Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
2002	A	`conf`	Topologically constrained logic synthesis. ICCAD Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
2002	A	`conf`	Using Problem Symmetry in Search Based Satisfiability Algorithms. DATE Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton
2002	A	`conf`	Whirlpool PLAs: a regular logic structure and their synthesis. ICCAD Fan Mo, Robert K. Brayton
2001	A	`conf`	A Force-Directed Maze Router. ICCAD Fan Mo, Abdallah Tabbara, Robert K. Brayton
2001	C	`conf`	A Timing-Driven Macro-Cell Placement Algorithm. ICCD Fan Mo, Abdallah Tabbara, Robert K. Brayton
2001	A	`conf`	Compatible Observability Don't Cares Revisited. ICCAD Robert K. Brayton
2001	—	`conf`	Logic optimization and code generation for embedded control applications. CODES Yunjian Jiang, Robert K. Brayton
2001	J	`jnl`	Partial-Order Reduction in Symbolic State-Space Exploration. Formal Methods Syst. Des. Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani
2001	A	`conf`	Sequential SPFDs. ICCAD Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton
2001	A	`conf`	Solution of Parallel Language Equations for Logic Synthesis. ICCAD Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli
2001	J	`jnl`	Theory of safe replacements for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
2001	A	`conf`	Using SAT for combinational equivalence checking. DATE Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton
2000	A	`conf`	A Force-Directed Macro-Cell Placer. ICCAD Fan Mo, Abdallah Tabbara, Robert K. Brayton
2000	A*	`conf`	Area and search space control for technology mapping. DAC Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten
2000	C	`conf`	Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. ICCD Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2000	A	`conf`	Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. ICCAD Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2000	A	`conf`	Don't Cares and Multi-Valued Logic Network Minimization. ICCAD Yunjian Jiang, Robert K. Brayton
2000	J	`jnl`	Integration of retiming with architectural floorplanning. Integr. Abdallah Tabbara, Bassam Tabbara, Robert K. Brayton, A. Richard Newton
2000	J	`jnl`	Model-checking continous-time Markov chains. ACM Trans. Comput. Log. Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton
2000	J	`jnl`	Negative thinking in branch-and-bound: the case of unate covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2000	J	`jnl`	Performance planning. Integr. Ralph H. J. M. Otten, Robert K. Brayton
2000	J	`jnl`	Sequential synthesis using S1S. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
2000	J	`jnl`	Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks. Formal Methods Syst. Des. Stefano Quer, Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Ellen Sentovich, Robert K. Brayton
1999	A*	`conf`	A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. DAC Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli
1999	—	`conf`	Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems. VLSI Luca P. Carloni, Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1999	J	`jnl`	Equivalences for Fair Kripke Structures. Chic. J. Theor. Comput. Sci. Adnan Aziz, Felice Balarin, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1999	Misc	`conf`	Multi-Valued Logic Synthesis. VLSI Design Robert K. Brayton, Sunil P. Khatri
1999	A	`conf`	Probabilistic state space search. ICCAD Andreas Kuehlmann, Kenneth L. McMillan, Robert K. Brayton
1999	A*	`conf`	Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints. DAC Abdallah Tabbara, Robert K. Brayton, A. Richard Newton
1999	Misc	`conf`	Sequential Multi-Valued Network Simplification using Redundancy Removal. VLSI Design Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1999	A	`conf`	Timing-safe false path removal for combinational modules. ICCAD Yuji Kukimoto, Robert K. Brayton
1999	A	`conf`	Using Combinational Verification for Sequential Circuits. DATE Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton
1998	—	`conf`	A New Low-Cost Method for Identifying Untestable Path Delay Faults. Asian Test Symposium Zhongcheng Li, Yinghua Min, Robert K. Brayton
1998	A	`conf`	Combinational Verification based on High-Level Functional Specifications. DATE Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton
1998	A*	`conf`	Computing Reachable Control States of Systems Modeled with Uninterpreted Functions and Infinite Memory. CAV Adrian J. Isles, Ramin Hojati, Robert K. Brayton
1998	A*	`conf`	Delay-Optimal Technology Mapping by DAG Covering. DAC Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar
1998	Misc	`conf`	Efficient Verification and Synthesis using Design Commonalities. VLSI Design Gitanjali Swamy, Stephen A. Edwards, Robert K. Brayton
1998	A*	`conf`	Hierarchical Functional Timing Analysis. DAC Yuji Kukimoto, Robert K. Brayton
1998	A	`conf`	Implementation and use of SPFDs in optimizing Boolean networks. ICCAD Subarnarekha Sinha, Robert K. Brayton
1998	A	`conf`	On the optimization power of retiming and resynthesis transformations. ICCAD Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton
1998	A*	`conf`	Planning for Performance. DAC Ralph H. J. M. Otten, Robert K. Brayton
1998	A*	`conf`	Structural Symmetry and Model Checking. CAV Gurmeet Singh Manku, Ramin Hojati, Robert K. Brayton
1998	J	`jnl`	Theory and algorithms for face hypercube embedding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1998	A	`conf`	Wireplanning in logic synthesis. ICCAD Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1997	A	`conf`	A fast and robust exact algorithm for face embedding. ICCAD Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1997	A	`conf`	Approximate timing analysis of combinational circuits under the XBD0 model. ICCAD Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton
1997	C	`conf`	Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions. ICCD Rajeev K. Ranjan, Wilsin Gosti, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1997	A	`conf`	Efficient Identification of Non-Robustly Untestable Path Delay Faults. ITC Zhongcheng Li, Robert K. Brayton, Yinghua Min
1997	A*	`conf`	Exact Required Time Analysis via False Path Detection. DAC Yuji Kukimoto, Robert K. Brayton
1997	J	`jnl`	Explicit and implicit algorithms for binate covering problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tiziano Villa, Timothy Kam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1997	J	`jnl`	Implicit computation of compatible sets for state minimization of ISFSMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1997	A	`conf`	Negative thinking by incremental problem solving: application to unate covering. ICCAD Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1997	A*	`conf`	Partial-Order Reduction in Symbolic State Space Exploration. CAV Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani
1997	A	`conf`	Reachability analysis using partitioned-ROBDDs. ICCAD Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1997	A*	`conf`	STARI: A Case Study in Compositional and Hierarchical Timing Verification. CAV Serdar Tasiran, Robert K. Brayton
1997	A	`conf`	Sequential optimisation without state space exploration. ICCAD Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli
1997	J	`jnl`	Symbolic two-level minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1997	J	`jnl`	Theory and algorithms for state minimization of nondeterministic FSMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1997	C	`conf`	Timed Binary Decision Diagrams. ICCD Zhongcheng Li, Yuhong Zhao, Yinghua Min, Robert K. Brayton
1996	Misc	`conf`	A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	C	`conf`	Binary decision diagrams on network of workstation. ICCD Rajeev K. Ranjan, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	J	`jnl`	Combinational test generation using satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	B	`conf`	Decomposition Techniques for Efficient ROBDD Construction. FMCAD Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
1996	C	`conf`	Early Quantification and Partitioned Transition Relations. ICCD Ramin Hojati, Sriram C. Krishnan, Robert K. Brayton
1996	A*	`conf`	Engineering Change in a Non-Deterministic FSM Setting. DAC Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	A*	`conf`	High Performance BDD Package By Exploiting Memory Hiercharchy. DAC Jagesh V. Sanghavi, Rajeev K. Ranjan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	—	`conf`	Incremental re-encoding for symbolic traversal of product machines. EURO-DAC Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer, Robert K. Brayton, Ellen Sentovich
1996	C	`conf`	Latch Redundancy Removal Without Global Reset. ICCD Shaz Qadeer, Robert K. Brayton, Vigyan Singhal
1996	J	`jnl`	Permissible functions for multioutput components in combinational logic optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton
1996	A	`conf`	The case for retiming with explicit reset circuitry. ICCAD Vigyan Singhal, Sharad Malik, Robert K. Brayton
1996	B	`conf`	VIS. FMCAD Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
1996	A*	`conf`	VIS: A System for Verification and Synthesis. CAV Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
1996	J	`jnl`	Valid clock frequencies and their computation in wavepipelined circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1996	B	`conf`	Verification Using Uninterpreted Functions and Finite Instantiations. FMCAD Ramin Hojati, Adrian J. Isles, Desmond Kirkpatrick, Robert K. Brayton
1996	B	`conf`	Verifying Abstractions of Timed Systems. CONCUR Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, Robert K. Brayton
1996	A*	`conf`	Verifying Continuous Time Markov Chains. CAV Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton
1995	J	`jnl`	An Environment for Formal Verification Based on Symbolic Computations. Formal Methods Syst. Des. Ramin Hojati, Robert K. Brayton
1995	J	`jnl`	An efficient heuristic procedure for solving the state assignment problem for event-based specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1995	A*	`conf`	Automatic Datapath Abstraction In Hardware Systems. CAV Ramin Hojati, Robert K. Brayton
1995	—	`conf`	Decomposition of logic functions for minimum transition activity. ED&TC Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1995	J	`jnl`	Delay fault coverage, test set size, and performance trade-offs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1995	—	`conf`	Exploiting power-up delay for sequential optimization. EURO-DAC Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
1995	Misc	`conf`	Functional clock schedule optimization. VLSI Design Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1995	C	`conf`	Implicit state minimization of non-deterministic FSMs. ICCD Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1995	C	`conf`	Incremental methods for FSM traversal. ICCD Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal
1995	—	`conf`	Language containment of non-deterministic CHARME Serdar Tasiran, Ramin Hojati, Robert K. Brayton
1995	A	`conf`	Multi-level logic optimization of FSM networks. ICCAD Huey-Yih Wang, Robert K. Brayton
1995	J	`jnl`	Network Hierarchies and Node Minimization. IEICE Trans. Inf. Syst. Robert K. Brayton, Ellen M. Sentovich
1995	C	`conf`	Power-Up Delay for Retiming Digital Circuits. ISCAS Vigyan Singhal, Robert K. Brayton, Carl Pixley
1995	A	`conf`	Sequential synthesis using S1S. ICCAD Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1995	A	`conf`	Structural Complexity of Omega-Automata. STACS Sriram C. Krishnan, Anuj Puri, Robert K. Brayton
1995	A*	`conf`	Supervisory Control of Finite State Machines. CAV Adnan Aziz, Felice Balarin, Robert K. Brayton, Marika Domenica Di Benedetto, Alexander Saldanha
1995	J	`jnl`	Testing Language Containment for omega-Automata Using BDD's Inf. Comput. Hervé J. Touati, Robert K. Brayton, Robert P. Kurshan
1995	A*	`conf`	The Rabin Index and Chain Automata, with Applications to Automatas and Games. CAV Sriram C. Krishnan, Anuj Puri, Robert K. Brayton, Pravin Varaiya
1995	A*	`conf`	The Validity of Retiming Sequential Circuits. DAC Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton
1994	A*	`conf`	A Fully Implicit Algorithm for Exact State Minimization. DAC Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	A	`conf`	A redesign technique for combinational circuits based on gate reconnections. ICCAD Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton
1994	C	`conf`	An Exact Optimization of Two-Level Acyclic Sequential Circuits. ICCD Ellen Sentovich, Robert K. Brayton
1994	A*	`conf`	BDD Variable Ordering for Interacting Finite State Machines. DAC Adnan Aziz, Serdar Tasiran, Robert K. Brayton
1994	J	`jnl`	Circuit structure relations to redundancy and delay. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	A*	`conf`	Criteria for the Simple Path Property in Timed Automata. CAV William K. C. Lam, Robert K. Brayton
1994	B	`conf`	Deterministic w Automata vis-a-vis Deterministic Buchi Automata. ISAAC Sriram C. Krishnan, Anuj Puri, Robert K. Brayton
1994	A*	`conf`	Equivalences for Fair Kripke Structures. ICALP Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	A*	`conf`	Exact Minimum Cycle Times for Finite State Machines. DAC William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	A*	`conf`	HSIS: A BDD-Based Environment for Formal Verification. DAC Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	A*	`conf`	Heuristic Minimization of BDDs Using Don't Cares. DAC Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
1994	A*	`conf`	Improving Language Containment Using Fairness Graphs. CAV Ramin Hojati, Robert B. Mueller-Thuns, Robert K. Brayton
1994	A	`conf`	Incremental formal design verification. ICCAD Gitanjali Swamy, Robert K. Brayton
1994	C	`conf`	Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. ICCD Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton
1994	A	`conf`	Multi-level synthesis for safe replaceability. ICCAD Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton
1994	A*	`conf`	Optimum Functional Decomposition Using Encoding. DAC Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	A*	`conf`	Performance Optimization Using Exact Sensitization. DAC Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	A*	`conf`	Permissible Observability Relations in FSM Networks. DAC Huey-Yih Wang, Robert K. Brayton
1994	J	`jnl`	Satisfaction of input and output encoding constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	J	`jnl`	Specification, synthesis, and verification of hazard-free asynchronous circuits. J. VLSI Signal Process. Cho W. Moon, Paul R. Stephan, Robert K. Brayton
1994	—	`conf`	State Minimization of Pseudo Non-Deterministic FSM's. EDAC-ETC-EUROASIC Yosinori Watanabe, Robert K. Brayton
1994	—	`book`	Timed Boolean functions - a unified formalism for exact timing analysis. William K. C. Lam, Robert K. Brayton
1993	A*	`conf`	A Unified Approach to Language Containment and Fair CTL Model Checking. DAC Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan
1993	A*	`conf`	Alternating RQ Timed Automata. CAV William K. C. Lam, Robert K. Brayton
1993	A*	`conf`	BDD-Based Debugging Of Design Using Language Containment and Fair CTL. CAV Ramin Hojati, Robert K. Brayton, Robert P. Kurshan
1993	A*	`conf`	Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions. DAC William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	J	`jnl`	Computing the initial states of retimed circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hervé J. Touati, Robert K. Brayton
1993	A	`conf`	Cube-packing and two-level minimization. ICCAD Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	A*	`conf`	Delay Fault Coverage and Performance Tradeoffs. DAC William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	—	`conf`	Dynamic variable reordering for BDD minimization. EURO-DAC Eric Felt, Gary York, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	J	`jnl`	ESPRESSO-SIGNATURE: a new exact minimizer for logic functions. IEEE Trans. Very Large Scale Integr. Syst. Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	A*	`conf`	Elimination of Dynamic hazards by Factoring. DAC Cho W. Moon, Robert K. Brayton
1993	A*	`conf`	Espresso-Signature: A New Exact Minimizer for Logic Functions. DAC Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	C	`conf`	Heuristic Minimization of Synchronous Relations. ICCD Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton
1993	J	`jnl`	Heuristic minimization of multiple-valued relations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yosinori Watanabe, Robert K. Brayton
1993	A	`conf`	Input don't care sequences in FSM networks. ICCAD Huey-Yih Wang, Robert K. Brayton
1993	C	`conf`	Logic Optimization with Multi-Output Gates. ICCD Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton
1993	A*	`conf`	Logic Synthesis and Design Verification. CAV Robert K. Brayton
1993	Misc	`conf`	Minimization of Logic Functions Using Essential Signature Sets. VLSI Design Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	A	`conf`	Minimum padding to satisfy short path constraints. ICCAD Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	A*	`conf`	On Computing the Transitive Closure of a State Transition Relation. DAC Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton
1993	J	`jnl`	Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	C	`conf`	Physically Realizable Gate Models. ICCD Paul R. Stephan, Robert K. Brayton
1993	A*	`conf`	Resynthesis of Multi-Phase Pipelines. DAC Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	A*	`conf`	Sequential Synthesis for Table Look Up Programmable Gate Arrays. DAC Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	C	`conf`	Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. ICCD Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	A	`conf`	The maximum set of permissible behaviors for FSM networks. ICCAD Yosinori Watanabe, Robert K. Brayton
1993	J	`jnl`	Two-Level Minimization of Multivalued Functions with Large Offsets. IEEE Trans. Computers Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1992	A*	`conf`	An Improved Synthesis Algorithm for Multiplexor-Based PGA's. DAC Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A*	`conf`	Automatic Reduction in CTL Compositional Model Checking. CAV Thomas R. Shiple, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
1992	A	`conf`	Automatic compositional minimization in CTL model checking. ICCAD Massimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
1992	—	`conf`	Boolean matching in logic synthesis. EURO-DAC Hamid Savoj, Mário J. Silva, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A*	`conf`	Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. DAC Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	C	`conf`	Delay Prediction for Technology-Independent Logic Equations. ICCD Paul T. Gutwin, Patrick C. McGeer, Robert K. Brayton
1992	A*	`conf`	Efficient CAV Ramin Hojati, Hervé J. Touati, Robert P. Kurshan, Robert K. Brayton
1992	A*	`conf`	Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. DAC Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A	`conf`	Graph algorithms for clock schedule optimization. ICCAD Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	C	`conf`	On Relationship Between ITE and BDD. ICCD William K. C. Lam, Robert K. Brayton
1992	A*	`conf`	On the Temporal Equivalence of Sequential Circuits. DAC Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	C	`conf`	Sequential Circuit Design Using Synthesis and Optimization. ICCD Ellen Sentovich, Kanwar Jit Singh, Cho W. Moon, Hamid Savoj, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A*	`conf`	Solving the State Assignment Problem for Signal Transition Graphs. DAC Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	J	`jnl`	Symbolic minimization of multilevel logic and the input encoding problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sharad Malik, Luciano Lavagno, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A	`conf`	Valid clocking in wavepipelined circuits. ICCAD William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	A*	`conf`	A Framework for Satisfying Input and Output Encoding Constraints. DAC Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	A	`conf`	Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing. ICCAD Hervé J. Touati, Hamid Savoj, Robert K. Brayton
1991	A	`conf`	Extracting Local Don't Cares for Network Optimization. ICCAD Hamid Savoj, Robert K. Brayton, Hervé J. Touati
1991	A	`conf`	Heuristic Minimazation of Multiple-Valued Relations. ICCAD Yosinori Watanabe, Robert K. Brayton
1991	A	`conf`	Improved Logic Synthesis Algorithms for Table Look Up Architectures. ICCAD Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	C	`conf`	Incremental Synthesis for Engineering Changes. ICCD Yosinori Watanabe, Robert K. Brayton
1991	A	`conf`	Observability Relations and Observability Don't Cares. ICCAD Hamid Savoj, Robert K. Brayton
1991	A	`conf`	On Clustering for Minimum Delay/Area. ICCAD Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	A	`conf`	Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. ICCAD Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	A	`conf`	Performance Enhancement through the Generalized Bypass Transform. ICCAD Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Sartaj Sahni
1991	—	`conf`	Preserving Don't Care Conditions During Retiming. VLSI Ellen Sentovich, Robert K. Brayton
1991	J	`jnl`	Reduced offsets for minimization of binary-valued functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1991	J	`jnl`	Retiming and resynthesis: optimizing sequential networks with combinational techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	C	`conf`	Retiming of Circuits with Single Phase Transparent Latches. ICCD Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	A	`conf`	Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. ICCAD Cho W. Moon, Paul R. Stephan, Robert K. Brayton
1991	C	`conf`	Three-Level Decomposition with Application to PLDs. ICCD Abdul A. Malik, David Harrison, Robert K. Brayton
1991	A	`conf`	Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. ICCAD Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1990	A	`conf`	Algorithms for Discrete Function Manipulation. ICCAD Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton
1990	A	`conf`	Implicit State Enumeration of Finite State Machines Using BDDs. ICCAD Hervé J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1990	A*	`conf`	Logic Synthesis for Programmable Gate Arrays. DAC Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1990	A	`conf`	MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. ICCAD Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1990	J	`jnl`	Multilevel logic synthesis. Proc. IEEE Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli
1990	A	`conf`	Performance Optimization of Pipelined Circuits. ICCAD Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1990	A*	`conf`	Reduced Offsets for Two-Level Multi-Valued Logic Minimization. DAC Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1990	A*	`conf`	The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks. DAC Hamid Savoj, Robert K. Brayton
1990	C	`conf`	The observability don't-care set and its approximations. ICCD Patrick C. McGeer, Robert K. Brayton
1990	A*	`conf`	Timing Analysis in Precharge/Unate Networks. DAC Patrick C. McGeer, Robert K. Brayton
1990	A	`conf`	Timing Optimization with Testability Considerations. ICCAD Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng
1989	A	`conf`	An exact minimizer for Boolean relations. ICCAD Robert K. Brayton, Fabio Somenzi
1989	A	`conf`	Consistency and observability invariance in multi-level logic synthesis. ICCAD Patrick C. McGeer, Robert K. Brayton
1989	A*	`conf`	Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network. DAC Patrick C. McGeer, Robert K. Brayton
1989	A*	`conf`	Efficient Prime Factorization of Logic Expressions. DAC Patrick C. McGeer, Robert K. Brayton
1989	A	`conf`	Fast two-level logic minimizers for multi-level logic synthesis. ICCAD Hamid Savoj, Abdul A. Malik, Robert K. Brayton
1989	C	`conf`	Logic minimization for factored forms. ICCD Abdul A. Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1989	A*	`conf`	Multi-level Logic Simplification Using Don't Cares and Filters. DAC Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1989	A	`conf`	SLIP: a software environment for system level interactive partitioning. ICCAD Mark Beardslee, Chuck Kring, Rajeev Murgai, Hamid Savoj, Robert K. Brayton, A. Richard Newton
1988	A	`conf`	A modified approach to two-level logic minimization. ICCAD Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1988	A	`conf`	Don't cares and global flow analysis of Boolean networks. ICCAD Robert K. Brayton, Ellen M. Sentovich, Fabio Somenzi
1988	A	`conf`	Logic verification using binary decision diagrams in a logic synthesis environment. ICCAD Sharad Malik, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1988	J	`jnl`	Multi-level logic minimization using implicit don't cares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
1988	A	`conf`	Timing optimization of combinational logic. ICCAD Kanwar Jit Singh, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1988	A	`conf`	XPSim: a MOS VLSI simulator. ICCAD Romy L. Bauer, Jiayuan Fang, Antony P.-C. Ng, Robert K. Brayton
1987	J	`jnl`	MIS: A Multiple-Level Logic Optimization System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
1986	J	`jnl`	Correction to "Optimal State Assignment for Finite State Machines". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1985	J	`jnl`	Optimal State Assignment for Finite State Machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1984	—	`book`	Logic Minimization Algorithms for VLSI Synthesis Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli
1964	J	`jnl`	Stability Criteria for Large Networks. IBM J. Res. Dev. Robert K. Brayton
1963	J	`jnl`	An Analysis of the Effect of Component Tolerances on the Amplification of the Balanced-Pair Tunnel-Diode Circuit. IEEE Trans. Electron. Comput. Robert K. Brayton, Ralph A. Willoughby