Robert H. Klenke

36 papers A* 3A 4B 1Misc 2Journal 9Unranked 16

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	A multilevel cybersecurity and safety monitor for embedded cyber-physical systems: WIP abstract. ICCPS Smitha Gautham, Georgios Bakirtzis, Matthew T. Leccadito, Robert H. Klenke, Carl R. Elks
2018	J	`jnl`	A Multilevel Cybersecurity and Safety Monitor for Embedded Cyber-Physical Systems. CoRR Smitha Gautham, Georgios Bakirtzis, Matthew T. Leccadito, Robert H. Klenke, Carl R. Elks
2013	—	`conf`	Initial evaluation of an IEEE 802.11s-based mobile ad-hoc network for collaborative Unmanned Aerial Vehicles. ICCVE Siva Teja Patibandla, Tim Bakker, Robert H. Klenke
2013	—	`conf`	RAMS: a fast, low-fidelity, multiple agent discrete-event simulator. SummerSim Tim Bakker, Garrett L. Ward, Siva T. Patibandla, Robert H. Klenke
2011	—	`conf`	Introducing MicroBlaze as an infrastructure for performance modeling. MSE Fadi Obeidat, Robert H. Klenke
2011	A	`conf`	Microblaze: an application-independent fpga-based profiler (abstract only). FPGA Fadi Obeidat, Robert H. Klenke
2010	—	`conf`	Application-Independent FPGA-based Profiling. ERSA Fadi Obeidat, Robert H. Klenke
2010	A	`conf`	Embedded Systems Performance Modeling using FPGA-based Profiling. ESA Fadi Obeidat, Jose Ortiz, Jeremy Cooper, Assem A. R. Bsoul, Robert H. Klenke
2007	—	`conf`	Experiences Using the Xilinx Microblaze Softcore Processor and uCLinux in Computer Engineering Capstone Senior Design Projects. MSE Robert H. Klenke
2005	—	`conf`	A UAV-Based Computer Engineering Capstone Senior Design Project. MSE Robert H. Klenke
2005	—	`conf`	Design and fabrication of a digitally synthesized, digitally controlled ring oscillator. Circuits, Signals, and Systems Sam Mitchum, Robert H. Klenke
2003	—	`conf`	A New Hardware/Software Codesign Environment and Senior Capstone Design Project for Computer Engineering. MSE Robert H. Klenke, Jerry H. Tucker, Jason M. Blevins
2003	—	`conf`	A Proposed Modeling Environment to Teach Performance Modeling and Hardware/Software Codesign to Senior Undergraduates. MSE Robert H. Klenke, James H. Aylor
2003	—	`conf`	Performance-Based System Design Education. MSE Jason J. Hein, James H. Aylor, Robert H. Klenke
2003	J	`jnl`	Teaching computer design using virtual prototyping. IEEE Trans. Educ. Ronald D. Williams, Robert H. Klenke, James H. Aylor
2001	—	`conf`	A Hardware/Software Codesign Senior Capstone Design Project in Computer Engineering. MSE Robert H. Klenke
2001	—	`conf`	Design of a 32-Bit Microprocessor in an Undergraduate VLSI Design Course. MSE Robert H. Klenke
2001	J	`jnl`	Interfaces for mixed-level simulation with sequential elements. J. Syst. Archit. Robert H. Klenke, James H. Aylor, Moshe Meyassed, William W. Dungan
2001	J	`jnl`	Performance Modeling of Hierarchical Crossbar-Based Multicomputer Systems. IEEE Trans. Computers Gang Han, Robert H. Klenke, James H. Aylor
2000	J	`jnl`	Dynamic Access Ordering for Streamed Computations. IEEE Trans. Computers Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle
2000	—	`conf`	System level testability analysis using Petri nets. HLDVT Tianjing Jiang, Robert H. Klenke, James H. Aylor, Gang Han
1999	A*	`conf`	Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory. HPCA Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf
1999	—	`ch.`	Performance Modeling and Analysis in VHDL. The VLSI Handbook James H. Aylor, Robert H. Klenke
1999	J	`jnl`	Resolving unknown inputs in mixed-level simulation with sequential elements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Moshe Meyassed, Robert H. Klenke, James H. Aylor
1998	A*	`conf`	A Top-Down Design Environment for Developing Pipelined Datapaths. DAC Robert M. McGraw, James H. Aylor, Robert H. Klenke
1998	J	`jnl`	Smarter Memory: Improving Bandwidth for Streamed References. Computer Sally A. McKee, Robert H. Klenke, Kenneth L. Wright, William A. Wulf, Maximo H. Salinas, James H. Aylor, Alan P. Batson
1997	A*	`conf`	An Integrated Design Environment for Performance and Dependability Analysis. DAC Robert H. Klenke, Moshe Meyassed, James H. Aylor, Barry W. Johnson, Ramesh Rao, Anup Ghosh
1997	—	`conf`	An undergraduate advanced computer design course using virtual-prototyping. MSE Robert H. Klenke, James H. Aylor
1996	J	`jnl`	An analysis of fault partitioned parallel test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Joseph M. Wolf, Lori M. Kaufman, Robert H. Klenke, James H. Aylor, Ronald Waxman
1996	Misc	`conf`	An analysis of fault partitioning algorithms for fault partitioned ATPG. VTS Robert H. Klenke, James H. Aylor, Joseph M. Wolf
1996	A	`conf`	Design and Evaluation of Dynamic Access Ordering Hardware. International Conference on Supercomputing Sally A. McKee, Assaji Aluwihare, Benjamin H. Clark, Robert H. Klenke, Trevor C. Landon, Christopher W. Oliver, Maximo H. Salinas, Adam E. Szymkowiak, Kenneth L. Wright, William A. Wulf, James H. Aylor
1995	B	`conf`	Refinement of system-level designs using hybrid modeling. ICECCS Robert M. McGraw, Moshe Meyassed, Robert H. Klenke, James H. Aylor, Ronald D. Williams
1994	—	`conf`	Experimental Implementation of Dynamic Access Ordering. HICSS (1) Sally A. McKee, Robert H. Klenke, Andrew J. Schwab, William A. Wulf, Steven A. Moyer, James H. Aylor, Charles Y. Hitchcock
1993	Misc	`conf`	Parallelization methods for circuit partitioning based parallel automatic test pattern generation. VTS Robert H. Klenke, Ronald D. Williams, James H. Aylor
1993	A	`conf`	Workstation Based Parallel Test Generation. ITC Robert H. Klenke, Lori M. Kaufman, James H. Aylor, Ronald Waxman, Padmini Narayan
1992	J	`jnl`	Parallel-Processing Techniques for Automatic Test Pattern Generation. Computer Robert H. Klenke, Ronald D. Williams, James H. Aylor