Robert Giterman

35 papers A 1C 8Misc 1Journal 19Unranked 6

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time. IEEE J. Solid State Circuits Odem Harel, Halil Andaç Yigit, Eliana Feifel, Robert Giterman, Andreas Burg, Adam Teman
2021	J	`jnl`	Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads. IEEE Access Yoav Weizman, Robert Giterman, Oron Chertkow, Maoz Wicentowski, Itamar Levi, Ilan Sever, Ishai Kehati, Osnat Keren, Alexander Fish
2021	J	`jnl`	Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros. IEEE Access Roman Golman, Netanel Nachum, Tomer Cohen, Robert Giterman, Adam Teman
2020	J	`jnl`	Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg
2020	C	`conf`	GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI. ISCAS Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
2020	C	`conf`	Gain-Cell Embedded DRAMs: Modeling and Design Space. ISCAS Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
2020	J	`jnl`	Gain-Cell Embedded DRAMs: Modeling and Design Space. IEEE Trans. Very Large Scale Integr. Syst. Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
2020	C	`conf`	Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique. ISCAS Roman Golman, Robert Giterman, Odem Harel, Adam Teman
2020	Misc	`conf`	Lupulus: A Flexible Hardware Accelerator for Neural Networks. ICASSP Andreas Toftegaard Kristensen, Robert Giterman, Alexios Balatsoukas-Stimming, Andreas Burg
2020	J	`jnl`	Lupulus: A Flexible Hardware Accelerator for Neural Networks. CoRR Andreas Toftegaard Kristensen, Robert Giterman, Alexios Balatsoukas-Stimming, Andreas Burg
2020	J	`jnl`	Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM. Microelectron. J. Odem Harel, Yarden Nachum, Robert Giterman
2019	—	`conf`	A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. A-SSCC Jonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici
2019	J	`jnl`	A 7T Security Oriented SRAM Bitcell. IEEE Trans. Circuits Syst. II Express Briefs Robert Giterman, Osnat Keren, Alexander Fish
2019	J	`jnl`	GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI. IEEE Trans. Circuits Syst. II Express Briefs Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
2019	J	`jnl`	Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection. IEEE Access Robert Giterman, Roman Golman, Adam Teman
2019	—	`conf`	Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications. ESSCIRC Robert Giterman, Maoz Wicentowski, Oron Chertkow, Ilan Sever, Ishai Kehati, Yoav Weizman, Osnat Keren, Alexander Fish
2018	J	`jnl`	A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI. IEEE Trans. Circuits Syst. I Regul. Pap. Robert Giterman, Alexander Fish, Andreas Burg, Adam Teman
2018	C	`conf`	A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing. ISCAS Or Maltabashi, Hanan Marinberg, Robert Giterman, Adam Teman
2018	J	`jnl`	An 800-MHz Mixed- V IEEE J. Solid State Circuits Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman
2018	—	`conf`	Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. ICECS Roman Golman, Robert Giterman, Adam Teman
2018	J	`jnl`	Gain-Cell Embedded DRAM-Based Physical Unclonable Function. IEEE Trans. Circuits Syst. I Regul. Pap. Robert Giterman, Yoav Weizman, Adam Teman
2018	—	`conf`	High Density GC-eDRAM Design in 16nm FinFET. ICECS Amir Shalom, Robert Giterman, Adam Teman
2018	J	`jnl`	Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell. IEEE Trans. Very Large Scale Integr. Syst. Robert Giterman, Maoz Vicentowski, Itamar Levi, Yoav Weizman, Osnat Keren, Alexander Fish
2018	C	`conf`	Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications. ISCAS Robert Giterman, Roman Golman, Amir Shalom, Or Maltabashi, Alexander Fish, Adam Teman
2017	—	`conf`	An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. ESSCIRC Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman
2017	J	`jnl`	Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. Robert Giterman, Lior Atias, Adam Teman
2017	J	`jnl`	Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation. IEEE Trans. Circuits Syst. II Express Briefs Robert Giterman, Adam Teman, Pascal Meinerzhagen
2017	C	`conf`	Ultra miniature offset cancelled bandgap reference with ±0.534% inaccuracy from -10°C to 110°C. ISCAS Natan Vinshtok-Melnik, Robert Giterman, Joseph Shor
2016	J	`jnl`	A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications. IEEE Trans. Very Large Scale Integr. Syst. Lior Atias, Adam Teman, Robert Giterman, Pascal Meinerzhagen, Alexander Fish
2016	C	`conf`	A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design. ISCAS Robert Giterman, Adam Teman, Pascal Meinerzhagen, Alexander Fish, Andreas Burg
2016	J	`jnl`	Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Lior Atias, Andreas Burg, Alexander Fish
2015	—	`conf`	Approximate computing with unreliable dynamic memories. NEWCAS Shrikanth Ganapathy, Adam Teman, Robert Giterman, Andreas Burg, Georgios Karakonstantis
2015	A	`conf`	Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. DATE Adam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Andreas Meinerzhagen, Andreas Peter Burg
2014	C	`conf`	4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. ISCAS Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Andreas Burg, Alexander Fish
2014	J	`jnl`	Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. IEEE Trans. Circuits Syst. II Express Briefs Adam Teman, Pascal Andreas Meinerzhagen, Robert Giterman, Alexander Fish, Andreas Burg