Robert Gauthier

16 papers A 1Journal 7Unranked 8
YearRankTypeTitle / Venue / Authors
2021 — conf
Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp.
IRPS
Sagar Premnath Karalkar, Vishal Ganesan, Milova Paul, Kyong Jin Hwang, Robert Gauthier
2020 — conf
Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology.
IRPS
Kyong Jin Hwang, Sagar Premnath Karalkar, Vishal Ganesan, Sevashanmugam Marimuthu, Alban Zaka, Tom Herrmann, Bhoopendra Singh, Robert Gauthier
2020 — conf
ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies.
CICC
You Li, Meng Miao, Robert Gauthier
2020 — conf
Understanding ESD Induced Thermal Mechanism in FinFETs Through Predictive TCAD Simulation.
IRPS
Zhiqing Li, Baofu Zhu, Anindya Nath, Meng Miao, Alain Loiseau, You Li, Jeffrey B. Johnson, Souvick Mitra, Robert Gauthier
2019 — conf
A Novel HV-NPN ESD Protection Device with Buried Floating P-Type Implant.
IRPS
Jie Jack Zeng, Ruchil Jain, Kyong Jin Hwang, Robert Gauthier
2017 — conf
Investigation of diode triggered silicon control rectifier turn-on time during ESD events.
SoCC
Ahmed Y. Ginawi, Robert Gauthier, Tian Xia
2014 — conf
Reducing the turn-on time and overshoot voltage for a diode-triggered silicon-controlled rectifier during an electrostatic discharge event.
SoCC
Ahmed Ginawi, Tian Xia, Robert Gauthier
2010 — conf
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond.
ISSCC
Ali Khaki-Firooz, Kangguo Cheng, Basanth Jagannathan, Pranita Kulkarni, Jeffrey W. Sleight, Davood Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, Huiming Bu, Robert Gauthier, Bruce Doris, Ghavam G. Shahidi
2010 J jnl
Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology.
Microelectron. Reliab.
Tommaso Cilento, M. Schenkel, C. Yun, R. Mishra, Junjun Li, Kiran V. Chatty, Robert Gauthier
2009 J jnl
Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology.
Microelectron. Reliab.
David Alvarez, Kiran V. Chatty, Christian Russ, Michel J. Abou-Khalil, Junjun Li, Robert Gauthier, Kai Esmark, Ralph Halbach, Christopher Seguin
2009 J jnl
Reliability aspects of gate oxide under ESD pulse stress.
Microelectron. Reliab.
Adrien Ille, Wolfgang Stadler, Thomas Pompl, Harald Gossner, Tilo Brodbeck, Kai Esmark, Philipp Riess, David Alvarez, Kiran V. Chatty, Robert Gauthier, Alain Bravaix
2007 J jnl
Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs.
Microelectron. Reliab.
Ciaran J. Brennan, Kiran V. Chatty, Jeff Sloan, Paul Dunn, Mujahid Muhammad, Robert Gauthier
2007 J jnl
Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs.
Microelectron. Reliab.
Ciaran J. Brennan, Shunhua Chang, Min Woo, Kiran V. Chatty, Robert Gauthier
2006 J jnl
Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant.
Microelectron. Reliab.
David Alvarez, Michel J. Abou-Khalil, Christian Russ, Kiran V. Chatty, Robert Gauthier, D. Kontos, Junjun Li, Christopher Seguin, Ralph Halbach
2003 J jnl
Latchup Analysis Using Emission Microscopy.
Microelectron. Reliab.
Franco Stellari, Peilin Song, Moyra K. McManus, Alan J. Weger, Robert Gauthier, Kiran V. Chatty, Mujahid Muhammad, Pia N. Sanda, Philip Wu, Steven C. Wilson
2003 A conf
Optical and Electrical Testing of Latchup in I/O Interface Circuits.
ITC
Franco Stellari, Peilin Song, Moyra K. McManus, Robert Gauthier, Alan J. Weger, Kiran V. Chatty, Mujahid Muhammad, Pia N. Sanda