Robert Czerwinski

12 papers C 2Journal 4Unranked 6
YearRankTypeTitle / Venue / Authors
2016 J jnl
An IEC 61131-3-based PLC implemented by means of an FPGA.
Microprocess. Microsystems
Miroslaw Chmiel, Józef Kulisz, Robert Czerwinski, A. Krzyzyk, Marcin Rosol, Patryk Smolarek
2016 J jnl
State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers.
ACM Trans. Design Autom. Electr. Syst.
Robert Czerwinski, Dariusz Kania
2015 — conf
Performance analysis of a PMSM drive with torque and speed control.
MIXDES
Tomasz Rudnicki, Robert Czerwinski, Dariusz Polok, Andrzej Sikora
2013 — conf
FPGA Implementation of Programmable Logic Controller Compliant with EN 61131-3.
PDeS
Robert Czerwinski, Miroslaw Chmiel, Wojciech Wygrabek
2012 J jnl
Area and speed oriented synthesis of FSMs for PAL-based CPLDs.
Microprocess. Microsystems
Robert Czerwinski, Dariusz Kania
2010 — conf
A PC-based object simulator for supporting PLC software development.
PDeS
Józef Kulisz, Robert Czerwinski, Jan Mocha, Miroslaw Chmiel
2010 — conf
The virtual drum kit.
PDeS
Piotr Foltyn, Przemyslaw Flak, Robert Czerwinski, Tomasz Rudnicki
2009 C conf
CPLD-oriented Synthesis of Finite State Machines.
DSD
Robert Czerwinski, Dariusz Kania
2009 — conf
State assignment and logic optimization for finite state machines.
PDeS
Robert Czerwinski, Dariusz Kania
2009 — conf
State machine description oriented towards effective usage of vendor-independent synthesis tools.
PDeS
Robert Czerwinski, Józef Kulisz
2009 J jnl
Synthesis of finite state machines for CPLDs.
Int. J. Appl. Math. Comput. Sci.
Robert Czerwinski, Dariusz Kania
2005 C conf
State Assignment for PAL-based CPLDs.
DSD
Robert Czerwinski, Dariusz Kania