Robert B. Reese

19 papers A 2C 5Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
2015 J jnl
CE2016 steering committee: a short update.
Inroads
Susan Conry, Eric Durant, Herman Lam, Victor P. Nelson, Robert B. Reese
2015 C conf
CE2016: Updated computer engineering curriculum guidelines.
FIE
Eric Durant, John Impagliazzo, Susan Conry, Robert B. Reese, Herman Lam, Victor P. Nelson, Joseph L. Hughes, Weidong Liu, Junlin Lu, Andrew D. McGettrick
2014 C conf
Setting the stage for CE2016: A revised body of knowledge.
FIE
Eric Durant, John Impagliazzo, Susan Conry, Robert B. Reese, Mitchell A. Thornton, Herman Lam, Victor P. Nelson
2012 — conf
Uncle - An RTL Approach to Asynchronous Design.
ASYNC
Robert B. Reese, Scott C. Smith, Mitchell A. Thornton
2007 — book
Finite State Machine Datapath Design, Optimization, and Implementation
Justin Davis, Robert B. Reese
2006 — book
Introduction to Logic Synthesis using Verilog HDL
Robert B. Reese, Mitchell A. Thornton
2005 J jnl
A Coarse-Grain Phased Logic CPU.
IEEE Trans. Computers
Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
2005 J jnl
Early evaluation for performance enhancement in phased logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger
2004 J jnl
Cooperative and progressive design experience for embedded systems.
IEEE Trans. Educ.
Jerry W. Bruce, James C. Harden, Robert B. Reese
2004 — conf
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion.
ACM Great Lakes Symposium on VLSI
Kenneth Fazel, Lun Li, Mitchell A. Thornton, Robert B. Reese, Cherrice Traver
2003 — conf
A Coarse-Grain Phased Logic CPU.
ASYNC
Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
2003 — conf
A Fine-Grain Phased Logic CPU.
ISVLSI
Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
2003 A conf
PLFire: A Visualization Tool for Asynchronous Phased Logic Designs.
DATE
Kenneth Fazel, Mitchell A. Thornton, Robert B. Reese
2002 A conf
Generalized Early Evaluation in Self-Timed Circuits.
DATE
Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver
2001 C conf
Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation.
ICCD
Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
2000 C conf
OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet.
ICCD
Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha P. Chandrakasan
1999 — conf
User-configurable experimental design flows on the web: the ISCAS'99 experiments.
ISCAS (6)
Hemang Lavana, Franc Brglez, Robert B. Reese
1997 J jnl
Developing and Distributing Component-Level VHDL Models.
J. VLSI Signal Process.
J. Scott Calhoun, Vijay K. Madisetti, Robert B. Reese, Thomas Egolf
1993 C conf
A Comparison of Synchronous and Asynchronous FSMD Designs.
ICCD
Richard Auletta, Robert B. Reese, Cherrice Traver