Robert A. Walker

33 papers A* 4A 8C 2Misc 2Journal 8Unranked 9
YearRankTypeTitle / Venue / Authors
2011 — conf
MTASC: A Multithreaded Associative SIMD Processor.
IPDPS Workshops
Kevin Schaffer, Robert A. Walker
2008 A conf
Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems.
DATE
Ken W. Batcher, Robert A. Walker
2008 J jnl
Using Hardware Multithreading to Overcome Broadcast/Reduction Latency in an Associative SIMD Processor.
Parallel Process. Lett.
Kevin Schaffer, Robert A. Walker
2008 A conf
Using hardware multithreading to overcome broadcast/reduction latency in an associative SIMD processor.
IPDPS
Kevin Schaffer, Robert A. Walker
2007 A conf
A Prototype Multithreaded Associative SIMD Processor.
IPDPS
Kevin Schaffer, Robert A. Walker
2006 — conf
Interrupt Triggered Software Prefetching for Embedded CPU Instruction Cache.
IEEE Real Time Technology and Applications Symposium
Ken W. Batcher, Robert A. Walker
2005 — conf
A Scalable Pipelined Associative SIMD Array with Reconfigurable PE Interconnection Network for Embedded Applications.
IASTED PDCS
Hong Wang, Robert A. Walker
2004 A conf
A Scalable Associative Processor with Applications in Database and Image Processing.
IPDPS
Hong Wang, Lei Xie, Meiduo Wu, Robert A. Walker
2004 — conf
Cluster miss prediction for instruction caches in embedded networking applications.
ACM Great Lakes Symposium on VLSI
Kenneth W. Batcher, Robert A. Walker
2004 Misc conf
Cluster miss prediction with prefetch on miss for embedded CPU instruction caches.
CASES
Ken W. Batcher, Robert A. Walker
2003 A conf
Implementing a Scalable ASC Processor.
IPDPS
Hong Wang, Robert A. Walker
2002 A conf
Implementing Associative Search and Responder Resolution.
IPDPS
Meiduo Wu, Robert A. Walker, Jerry L. Potter
2001 A conf
Implementing Associative Processing: Rethinking EarlierArchitectural Decisions.
IPDPS
Robert A. Walker, Jerry L. Potter, Yanping Wang, Meiduo Wu
2000 J jnl
Efficient optimal design space characterization methodologies.
ACM Trans. Design Autom. Electr. Syst.
Stephen A. Blythe, Robert A. Walker
1999 A conf
A practical one-semester "VLSI design" course for computer science (and other) majors.
SIGCSE
Robert A. Walker
1999 — conf
Bounding Algorithms for Design Space Exploration.
Great Lakes Symposium on VLSI
Samit Chaudhuri, Robert A. Walker
1999 — conf
Efficiently Searching the Optimal Design Space.
Great Lakes Symposium on VLSI
Stephen A. Blythe, Robert A. Walker
1997 J jnl
A solution methodology for exact design space exploration in a three-dimensional design space.
IEEE Trans. Very Large Scale Integr. Syst.
Samit Chaudhuri, S. A. Blthye, Robert A. Walker
1996 J jnl
Computing lower bounds on functional units before scheduling.
IEEE Trans. Very Large Scale Integr. Syst.
Samit Chaudhuri, Robert A. Walker
1996 — conf
Toward a Practical Methodology for Completely Characterizing the Optimal Design Space.
ISSS
Stephen A. Blythe, Robert A. Walker
1995 — conf
An exact methodology for scheduling in a 3D design space.
ISSS
Samit Chaudhuri, Stephen A. Blythe, Robert A. Walker
1995 J jnl
Introduction to the Scheduling Problem.
IEEE Des. Test Comput.
Robert A. Walker, Samit Chaudhuri
1994 J jnl
Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem.
IEEE Trans. Very Large Scale Integr. Syst.
Samit Chaudhuri, Robert A. Walker, J. E. Mitchell
1994 — conf
Computing lower bounds on functional units before scheduling.
HLSS
Samit Chaudhuri, Robert A. Walker
1994 Misc conf
ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis.
VLSI Design
Samit Chaudhuri, Robert A. Walker
1993 C conf
Cluster-Oriented Scheduling in Pipelined Data Path Syntesis.
ICCD
Ching-Tang Chang, Kenneth Rose, Robert A. Walker
1993 C conf
The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem.
ICCD
Samit Chaudhuri, Robert A. Walker, John Mitchell
1991 A* conf
Increasing User Interaction During High-Level Synthesis.
MICRO
Robert A. Walker, Shivkumar Ramabadran, Rajive Joshi, Steinar Flatland
1989 J jnl
Behavioral transformation for algorithmic level IC design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Robert A. Walker, Donald E. Thomas
1988 A* conf
The System Architect's Workbench.
DAC
Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn
1985 A* conf
A model of design representation and synthesis.
DAC
Robert A. Walker, Donald E. Thomas
1983 J jnl
Automatic Data Path Synthesis.
Computer
Donald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, Robert A. Walker
1983 A* conf
Behavioral level transformation in the CMU-DA system.
DAC
Robert A. Walker, Donald E. Thomas