Rob A. Rutenbar

179 papers A* 36A 45B 7C 3Misc 10Journal 45Unranked 31
YearRankTypeTitle / Venue / Authors
2024 J jnl
Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers.
IEEE Trans. Very Large Scale Integr. Syst.
Sunwoong Kim, Cameron James Norris, James I. Oelund, Rob A. Rutenbar
2022 — conf
HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming.
ASAP
Adel Ejjeh, Leon Medvinsky, Aaron Councilman, Hemang Nehra, Suraj Sharma, Vikram S. Adve, Luigi Nardi, Eriko Nurvitadhi, Rob A. Rutenbar
2022 J jnl
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL.
CoRR
Adel Ejjeh, Vikram S. Adve, Rob A. Rutenbar
2020 — conf
A 3mm
VLSI Circuits
Glenn G. Ko, Yuji Chai, Marco Donato, Paul N. Whatmough, Thierry Tambe, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei
2020 — conf
A Scalable Bayesian Inference Accelerator for Unsupervised Learning.
Hot Chips Symposium
Glenn G. Ko, Yuji Chai, Marco Donato, Paul N. Whatmough, Thierry Tambe, Rob A. Rutenbar, Gu-Yeon Wei, David Brooks
2020 Misc conf
Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme.
FCCM
Sunwoong Kim, Keewoo Lee, Wonhee Cho, Yujin Nam, Jung Hee Cheon, Rob A. Rutenbar
2020 A conf
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL.
FPGA
Adel Ejjeh, Vikram S. Adve, Rob A. Rutenbar
2019 A conf
A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference.
FPGA
Tianqi Gao, Rob A. Rutenbar
2019 — conf
A Virtual Image Accelerator for Graph Cuts Inference on FPGA.
ASAP
Tianqi Gao, Rob A. Rutenbar
2019 B conf
Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling.
FPL
Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei
2019 — conf
An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA.
ACM Great Lakes Symposium on VLSI
Sunwoong Kim, Rob A. Rutenbar
2019 — conf
FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption.
ReConFig
Sunwoong Kim, Keewoo Lee, Wonhee Cho, Jung Hee Cheon, Rob A. Rutenbar
2019 Misc conf
FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs.
FCCM
Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei
2018 Misc conf
Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA.
FCCM
Sunwoong Kim, Rob A. Rutenbar
2018 J jnl
Real-Time and Low-Power Streaming Source Separation Using Markov Random Field.
ACM J. Emerg. Technol. Comput. Syst.
Glenn G. Ko, Rob A. Rutenbar
2018 J jnl
Realizing the potential of data science.
Commun. ACM
Francine Berman, Rob A. Rutenbar, Brent Hailpern, Henrik I. Christensen, Susan B. Davidson, Deborah Estrin, Michael J. Franklin, Margaret Martonosi, Padma Raghavan, Victoria Stodden, Alexander S. Szalay
2017 Misc conf
A case study of machine learning hardware: Real-time source separation using Markov Random Fields via sampling-based inference.
ICASSP
Glenn G. Ko, Rob A. Rutenbar
2017 B conf
Toward a pixel-parallel architecture for graph cuts inference on FPGA.
FPL
Tianqi Gao, Jungwook Choi, Shang-nien Tsai, Rob A. Rutenbar
2016 Misc conf
Analysis of error resiliency of belief propagation in computer vision.
ICASSP
Jungwook Choi, Ameya D. Patil, Rob A. Rutenbar, Naresh R. Shanbhag
2016 B conf
Configurable and scalable belief propagation accelerator for computer vision.
FPL
Jungwook Choi, Rob A. Rutenbar
2016 J jnl
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching.
IEEE Trans. Very Large Scale Integr. Syst.
Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar
2016 A conf
Keynote address Wednesday: Hardware inference accelerators for machine learning.
ITC
Rob A. Rutenbar
2016 J jnl
Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform.
IEEE Trans. Circuits Syst. Video Technol.
Jungwook Choi, Rob A. Rutenbar
2015 — conf
Analog Circuit and Layout Synthesis Revisited.
ISPD
Rob A. Rutenbar
2015 B conf
Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference.
FPL
Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, José F. Martínez, Rob A. Rutenbar
2014 Misc conf
A robust message passing based stereo matching kernel via system-level error resiliency.
ICASSP
Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar
2014 J jnl
DAC at 50: The Second 25 Years.
IEEE Des. Test
Rob A. Rutenbar
2014 A conf
Efficiently Enforcing Diversity in Multi-Output Structured Prediction.
AISTATS
Abner Guzmán-Rivera, Pushmeet Kohli, Dhruv Batra, Rob A. Rutenbar
2014 A* conf
The First EDA MOOC: Teaching Design Automation to Planet Earth.
DAC
Rob A. Rutenbar
2013 A* conf
Automatic clustering of wafer spatial signatures.
DAC
Wangyang Zhang, Xin Li, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar
2013 B conf
EMERALD: Characterization of emerging applications and algorithms for low-power devices.
ISPASS
Chuanjun Zhang, Glenn G. Ko, Jungwook Choi, Shang-nien Tsai, Minje Kim, Abner Guzmán-Rivera, Rob A. Rutenbar, Paris Smaragdis, Mi Sun Park, Vijaykrishnan Narayanan, Hongyi Xin, Onur Mutlu, Bin Li, Li Zhao, Mei Chen
2013 J jnl
Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar
2013 — conf
Error resilient MRF message passing architecture for stereo matching.
SiPS
Jungwook Choi, Eric P. Kim, Rob A. Rutenbar, Naresh R. Shanbhag
2013 C conf
FPGA acceleration of Markov Random Field TRW-S inference for stereo matching.
MEMOCODE
Jungwook Choi, Rob A. Rutenbar
2013 A conf
Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform.
FPGA
Jungwook Choi, Rob A. Rutenbar
2012 — conf
A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers.
ASAP
Jeffrey R. Johnston, Rob A. Rutenbar
2012 B conf
Hardware implementation of MRF map inference on an FPGA platform.
FPL
Jungwook Choi, Rob A. Rutenbar
2012 — conf
Spatial variation decomposition via sparse regression.
ICICDT
Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Emrah Acar, Frank Liu, Rob A. Rutenbar
2012 — conf
Stereophonic spectrogram segmentation using Markov random fields.
MLSP
Minje Kim, Paris Smaragdis, Glenn G. Ko, Rob A. Rutenbar
2011 A conf
Toward efficient spatial variation decomposition via sparse regression.
ICCAD
Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Rob A. Rutenbar
2011 J jnl
Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton
2010 — conf
Analog layout synthesis: what's missing?
ISPD
Rob A. Rutenbar
2010 A* conf
Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference.
DAC
Wangyang Zhang, Xin Li, Rob A. Rutenbar
2010 A conf
Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation.
ICCAD
Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob A. Rutenbar
2010 J jnl
Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun
2010 J jnl
Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Amith Singhee, Rob A. Rutenbar
2009 A conf
A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer.
FPGA
Edward C. Lin, Rob A. Rutenbar
2009 — book
Novel Algorithms for Fast Statistical Analysis of Scaled Circuits
Amith Singhee, Rob A. Rutenbar
2009 A* conf
Oil fields, hedge funds, and drugs.
DAC
Patrick Groeneveld, Rob A. Rutenbar, Jed W. Pitera, Erik C. Carlson, Jinsong Chen
2009 A conf
Profiling large-vocabulary continuous speech recognition on embedded devices: a hardware resource sensitivity analysis.
INTERSPEECH
Kai Yu, Rob A. Rutenbar
2009 J jnl
Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Amith Singhee, Rob A. Rutenbar
2009 A conf
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits.
ICCAD
Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton
2008 A conf
A low-power hardware search architecture for speech recognition.
INTERSPEECH
Patrick J. Bourke, Rob A. Rutenbar
2008 J jnl
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.
Proc. IEEE
Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard
2008 A conf
Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing.
DATE
Amith Singhee, Sonia Singhal, Rob A. Rutenbar
2008 A conf
Practical, fast Monte Carlo statistical static timing analysis: why and how.
ICCAD
Amith Singhee, Sonia Singhal, Rob A. Rutenbar
2008 J jnl
Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar
2008 Misc conf
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design.
VLSI Design
Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar
2008 A* conf
Verifying really complex systems: on earth and beyond.
DAC
Andreas Kuehlmann, Anjan Bose, David E. Corman, Rob A. Rutenbar, Robert M. Manning, Anna Newman
2007 A conf
A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA.
FPGA
Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen
2007 A* conf
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting.
DAC
Amith Singhee, Rob A. Rutenbar
2007 — conf
Collaborative VLSI-CAD Instruction in the Digital Sandbox.
MSE
Alex K. Jones, Steven P. Levitan, Rob A. Rutenbar, Yuan Xie
2007 J jnl
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters
CoRR
Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
2007 — conf
From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis.
ISQED
Amith Singhee, Rob A. Rutenbar
2007 A conf
Generating small, accurate acoustic models with a modified Bayesian information criterion.
INTERSPEECH
Kai Yu, Rob A. Rutenbar
2007 J jnl
Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs.
Proc. IEEE
Rob A. Rutenbar, Georges G. E. Gielen, Jaijeet S. Roychowdhury
2007 J jnl
Interval-Valued Reduced-Order Statistical Interconnect Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
James D. Ma, Rob A. Rutenbar
2007 — conf
Mixed-size placement with fixed macrocells using grid-warping.
ISPD
Zhong Xiu, Rob A. Rutenbar
2007 — conf
Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains.
ASP-DAC
Rob A. Rutenbar
2007 A conf
Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application.
DATE
Amith Singhee, Rob A. Rutenbar
2007 — conf
Statistical modeling for the minimum standby supply voltage of a full SRAM array.
ESSCIRC
Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun
2006 A conf
Design automation for analog: the next generation of tool challenges.
ICCAD
Rob A. Rutenbar
2006 J jnl
Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
James D. Ma, Rob A. Rutenbar
2006 A conf
Faster, parametric trajectory-based macromodels via localized linear reductions.
ICCAD
Saurabh K. Tiwary, Rob A. Rutenbar
2006 A* conf
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration.
DAC
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar
2006 — conf
In silico vox: Towards speech recognition in silicon.
Hot Chips Symposium
Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen
2006 A conf
Moving speech recognition from software to silicon: the in silico vox project.
INTERSPEECH
Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen
2006 — conf
On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels.
CICC
Saurabh K. Tiwary, Rob A. Rutenbar
2006 A* conf
Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools.
DAC
Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar
2006 A conf
Verifying analog oscillator circuits using forward/backward abstraction refinement.
DATE
Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar
2005 A conf
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters.
DATE
Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
2005 — conf
Early research experience with OpenAccess gear: an open source development environment for physical design.
ISPD
Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov
2005 — conf
Fast interval-valued statistical interconnect modeling and reduction.
ISPD
James D. Z. Ma, Rob A. Rutenbar
2005 A conf
Interval-valued statistical modeling of oxide chemical-mechanical polishing.
ICCAD
James D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning
2005 A* conf
Scalable trajectory methods for on-demand analog macromodel extraction.
DAC
Saurabh K. Tiwary, Rob A. Rutenbar
2005 — conf
Time Domain Verification of Oscillator Circuit Properties.
FAC
Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar, Oded Maler
2005 A* conf
Timing-driven placement by grid-warping.
DAC
Zhong Xiu, Rob A. Rutenbar
2004 J jnl
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints.
IEEE Trans. Computers
Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
2004 A* conf
A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits.
DAC
Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley
2004 A conf
Interval-valued reduced order statistical interconnect modeling.
ICCAD
James D. Ma, Rob A. Rutenbar
2004 A* conf
Large-scale placement by grid-warping.
DAC
Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar
2004 A conf
Static statistical timing analysis for latch-based pipeline designs.
ICCAD
Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu
2004 A conf
Towards formal verification of analog designs.
ICCAD
Smriti Gupta, Bruce H. Krogh, Rob A. Rutenbar
2004 A* conf
Will Moore's Law rule in the land of analog?
DAC
Rob A. Rutenbar, Anthony R. Bonaccio, Teresa H. Meng, Ernesto Perea, Robert Pitts, Charles G. Sodini, Jim Wieser
2003 A conf
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs.
ICCAD
Claire Fang Fang, Rob A. Rutenbar, Tsuhan Chen
2003 — conf
Floating-point error analysis based on affine arithmetic.
ICASSP (2)
Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar
2003 A* conf
Mixed signals on mixed-signal: the right next technology.
DAC
Rob A. Rutenbar, David L. Harame, Kurt Johnson, Paul Kempf, Teresa H. Meng, Reza Rofougaran, James Spoto
2003 A* conf
Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling.
DAC
Claire Fang Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen
2003 J jnl
sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hui Xu, Rob A. Rutenbar, Karem A. Sakallah
2002 J jnl
A new FPGA detailed routing approach via search-based Booleansatisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
2002 Misc conf
Floating-point bit-width optimization for low-power signal processing applications.
ICASSP
Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar
2002 B conf
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search.
FPL
Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
2002 J jnl
Lightweight Floating-Point Arithmetic: Case Study of Inverse Discrete Cosine Transform.
EURASIP J. Adv. Signal Process.
Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar
2002 A* conf
Remembrance of circuits past: macromodeling by data mining in large analog design spaces.
DAC
Hongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley
2002 — conf
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing.
ISPD
Hui Xu, Rob A. Rutenbar, Karem A. Sakallah
2001 A conf
A boolean satisfiability-based incremental rerouting approach with application to FPGAs.
DATE
Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
2001 — conf
A comparative study of two Boolean formulations of FPGA detailed routing constraints.
ISPD
Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
2001 A conf
ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits.
ICCAD
Michael Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, L. Richard Carley
2001 A conf
Automatic Hierarchical Design: Fantasy or Reality? (Panel).
ICCAD
Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni
2001 A conf
Direct Transistor-Level Layout for Digital Blocks.
ICCAD
Prakash Gopalakrishnan, Rob A. Rutenbar
2001 A conf
Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design.
ICCAD
Domine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen
2001 A conf
Low-power technology mapping for mixed-swing logic.
ISLPED
Rob A. Rutenbar, L. Richard Carley, Roberto Zafalon, Nicola Dragone
2001 A* conf
Panel: (When) Will FPGAs Kill ASICs?
DAC
Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen
2001 — conf
Synthesis for Industrial-Scale Analog Intellectual Property.
Evolvable Hardware
Rob A. Rutenbar
2001 J jnl
Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rony Kay, Rob A. Rutenbar
2000 A* conf
A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC.
DAC
Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums
2000 J jnl
Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums
2000 A* conf
Case studies: Chip design on the bleeding edge (panel session abstract).
DAC
John M. Cohn, Rob A. Rutenbar, Steve J. Young, Chris Malachowsky, Luis Aldaz
2000 J jnl
Computer-aided design of analog and mixed-signal integrated circuits.
Proc. IEEE
Georges G. E. Gielen, Rob A. Rutenbar
2000 J jnl
Efficient handling of operating range and manufacturing linevariations in analog cell synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar
2000 — conf
Layout tools for analog ICs and mixed-signal SoCs: a survey.
ISPD
Rob A. Rutenbar, John M. Cohn
2000 A* conf
Life at the end of CMOS scaling (and beyond) (panel session) (abstract only).
DAC
Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow
2000 J jnl
Reducing power by optimizing the necessary precision/range of floating-point arithmetic.
IEEE Trans. Very Large Scale Integr. Syst.
J. Y. F. Tong, David Nagle, Rob A. Rutenbar
2000 A* conf
Survival strategies for mixed-signal systems-on-chip (panel session).
DAC
Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy
2000 — conf
Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution.
ISPD
Rony Kay, Rob A. Rutenbar
1999 — conf
ANACONDA: robust synthesis of analog circuits via stochastic pattern search.
CICC
Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums
1999 J jnl
Device-level early floorplanning algorithms for RF circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley
1999 A conf
Inverse polarity techniques for high-speed/low-power multipliers.
ISLPED
Pascal C. H. Meier, Rob A. Rutenbar, L. Richard Carley
1999 A* conf
MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells.
DAC
Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley
1999 Misc conf
Satisfiability-Based Detailed FPGA Routing.
VLSI Design
Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
1999 A conf
Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT.
FPGA
Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
1998 — conf
Device-level early floorplanning algorithms for RF circuits.
ISPD
Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley
1998 J jnl
FPGA routing and routability estimation via Boolean satisfiability.
IEEE Trans. Very Large Scale Integr. Syst.
R. Glenn Wood, Rob A. Rutenbar
1998 J jnl
Performance-driven simultaneous placement and routing for FPGA's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sudip Nag, Rob A. Rutenbar
1997 A conf
A hierarchical decomposition methodology for multistage clock circuits.
ICCAD
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
1997 A conf
FPGA Routing and Routability Estimation via Boolean Satisfiability.
FPGA
R. Glenn Wood, Rob A. Rutenbar
1996 A* conf
An
DAC
Bülent Basaran, Rob A. Rutenbar
1996 A ed.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996
ICCAD
Rob A. Rutenbar, Ralph H. J. M. Otten
1996 A* conf
Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies.
DAC
L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen
1996 J jnl
Synthesis of high-performance analog circuits in ASTRX/OBLX.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley
1995 J jnl
Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization.
IEEE J. Solid State Circuits
Balsha R. Stanisic, Rob A. Rutenbar, L. Richard Carley
1995 J jnl
Integer programming based topology selection of cell-level analog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar
1995 A conf
Performance-driven simultaneous place and route for island-style FPGAs.
ICCAD
Sudip K. Nag, Rob A. Rutenbar
1995 J jnl
Reengineering the curriculum: design and analysis of a new undergraduate Electrical and Computer Engineering degree at Carnegie Mellon University.
Proc. IEEE
Stephen W. Director, Pradeep K. Khosla, Ronald A. Rohrer, Rob A. Rutenbar
1995 J jnl
Substrate-aware mixed-signal macrocell placement in WRIGHT.
IEEE J. Solid State Circuits
Sujoy Mitra, Rob A. Rutenbar, L. Richard Carley, David J. Allstot
1995 Misc conf
Testability-oriented channel routing.
VLSI Design
Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar
1994 A* conf
ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits.
DAC
Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley
1994 J jnl
Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis.
IEEE J. Solid State Circuits
Balsha R. Stanisic, Nishath K. Verghese, Rob A. Rutenbar, L. Richard Carley, David J. Allstot
1994 A* conf
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs.
DAC
Sudip Nag, Rob A. Rutenbar
1994 A conf
Synthesis of manufacturable analog circuits.
ICCAD
Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar
1993 A conf
Latchup-aware placement and parasitic-bounded routing of custom analog cells.
ICCAD
Bülent Basaran, Rob A. Rutenbar, L. Richard Carley
1992 A* conf
A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis.
DAC
Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar
1992 J jnl
Knowledge Representation and Reasoning in a Software Synthesis Architecture.
IEEE Trans. Software Eng.
Dorothy E. Setliff, Rob A. Rutenbar
1992 A conf
System-level routing of mixed-signal ASICs in WREN.
ICCAD
Sujoy Mitra, Sudip Nag, Rob A. Rutenbar, L. Richard Carley
1991 A conf
A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations.
ICCAD
Rajeev Jayaraman, Rob A. Rutenbar
1991 J jnl
KOAN/ANAGRAM II: new tools for device-level analog placement and routing.
IEEE J. Solid State Circuits
John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley
1991 J jnl
Massively parallel switch-level simulation: a feasibility study.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar
1991 J jnl
On the feasibility of synthesizing CAD software from specifications: generating maze router tools in ELF.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dorothy E. Setliff, Rob A. Rutenbar
1991 A conf
Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II.
ICCAD
John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley
1990 A* conf
Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW.
DAC
Erik C. Carlson, Rob A. Rutenbar
1989 A* conf
ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software.
DAC
Dorothy E. Setliff, Rob A. Rutenbar
1989 A* conf
Logic Simulation on Massively Parallel Architectures.
ISCA
Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar
1989 A* conf
Massively Parallel Switch-Level Simulation: A Feasibility Study.
DAC
Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar
1989 J jnl
OASYS: a framework for analog circuit synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
1989 — conf
Zen and the Art of Analog Design Automation.
IFIP Congress
Rob A. Rutenbar
1988 C conf
Analog circuit synthesis and exploration in OASYS.
ICCD
Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
1988 A conf
Analog circuit synthesis for performance in OASYS.
ICCAD
Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
1988 A conf
Automatic layout of custom analog cells in ANAGRAM.
ICCAD
David J. Garrod, Rob A. Rutenbar, L. Richard Carley
1988 A* conf
Mask Verification on the Connection Machine.
DAC
Erik C. Carlson, Rob A. Rutenbar
1988 J jnl
Systolic routing hardware: performance evaluation and optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rob A. Rutenbar, Daniel E. Atkins
1987 A* conf
A Prototype Framework for Knowledge-Based Analog Circuit Synthesis.
DAC
Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
1987 J jnl
A Scanline Data Structure Processor for VLSI Geometry Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Erik C. Carlson, Rob A. Rutenbar
1987 J jnl
Placement by Simulated Annealing on a Multiprocessor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Saul A. Kravitz, Rob A. Rutenbar
1986 A* conf
Multiprocessor-based placement by simulated annealing.
DAC
Saul A. Kravitz, Rob A. Rutenbar
1985 A* conf
Future directions for DA machine research (panel session).
DAC
Rob A. Rutenbar
1984 J jnl
A Class of Cellular Architectures to Support Physical Design Automation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rob A. Rutenbar, Trevor N. Mudge, Daniel E. Atkins
1984 — —
A Class of Cellular Computer Architectures to Support Physical Design Automation (Vlsi Layout, Integrated Circuit, Routing).
Rob A. Rutenbar
1982 A* conf
Cellular image processing techniques for VLSI circuit layout validation and routing.
DAC
Trevor N. Mudge, Rob A. Rutenbar, Robert M. Lougheed, Daniel E. Atkins
1981 C conf
Case study of a VLSI design project: A simple inner product machine.
IEEE Symposium on Computer Arithmetic
Rob A. Rutenbar, Y. E. Park