Rino Micheloni

44 papers A 1B 1Journal 21Unranked 14

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Addressing the Cross-Temperature Issue in 3-D NAND Flash Memories: Characterization and Mitigation for Solid-State Drives. IEEE Des. Test Cristian Zambelli, Rino Micheloni
2025	J	`jnl`	High throughput edit distance computation on FPGA-based accelerators using HLS. Future Gener. Comput. Syst. Sebastiano Fabio Schifano, Marco Reggiani, Enrico Calore, Rino Micheloni, Alessia Marelli, Cristian Zambelli
2025	—	`conf`	Leveraging Large-Scale TLC 3D NAND Flash Characterization to Investigate Early Lifetime Reliability of SSDs through Extreme Value Statistics. IRPS Rino Micheloni, Luca Crippa, Alessia Marelli, Lorenzo Zuolo, Piero Olivo, Cristian Zambelli
2023	J	`jnl`	An HPC Pipeline for Calcium Quantification of Aortic Root From Contrast-Enhanced CCT Scans. IEEE Access Giada Minghini, Armando Ugo Cavallo, Andrea Miola, Valentina Sisini, Enrico Calore, Francesca Fortini, Rino Micheloni, Paola Rizzo, Sebastiano Fabio Schifano, Francesco Vieceli Dalla Sega, Cristian Zambelli
2023	—	`conf`	Insights into device and material origins and physical mechanisms behind cross temperature in 3D NAND. IRPS Milan Pesic, Bastien Beltrando, Tommaso Rollo, Cristian Zambelli, Andrea Padovani, Rino Micheloni, Rita Maji, Lisa Enman, Mark Saly, Yang Ho Bae, Jung-Bae Kim, Dong Kil Yim, Luca Larcher
2023	J	`jnl`	Modeling 3D NAND Flash with Nonparametric Inference on Regression Coefficients for Reliable Solid-State Storage. Future Internet Michela Borghesi, Cristian Zambelli, Rino Micheloni, Stefano Bonnini
2021	—	`conf`	Logarithmic Non-uniform Quantization for List Decoding of Polar Codes. CCWC Mohammad Rowshan, Emanuele Viterbo, Rino Micheloni, Alessia Marelli
2020	J	`jnl`	A Novel Graph Expansion and a Decoding Algorithm for NB-LDPC Codes. IEEE Trans. Commun. Viduranga Bandara Wijekoon, Emanuele Viterbo, Yi Hong, Rino Micheloni, Alessia Marelli
2019	B	`conf`	Coset Probability Based Majority-logic Decoding for Non-binary LDPC Codes. ITW Viduranga Bandara Wijekoon, Shuiyin Liu, Emanuele Viterbo, Yi Hong, Rino Micheloni, Alessia Marelli
2019	J	`jnl`	Efficient Decoding of Low Density Lattice Codes. IEEE Wirel. Commun. Lett. Shuiyin Liu, Yi Hong, Emanuele Viterbo, Alessia Marelli, Rino Micheloni
2019	J	`jnl`	Enabling Computational Storage Through FPGA Neural Network Accelerator for Enterprise SSD. IEEE Trans. Circuits Syst. II Express Briefs Cristian Zambelli, Riccardo Bertaggia, Lorenzo Zuolo, Rino Micheloni, Piero Olivo
2019	J	`jnl`	LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives. IEEE Trans. Emerg. Top. Comput. Lorenzo Zuolo, Cristian Zambelli, Alessia Marelli, Rino Micheloni, Piero Olivo
2018	J	`jnl`	Fast Decoding of Low Density Lattice Codes. CoRR Shuiyin Liu, Yi Hong, Emanuele Viterbo, Alessia Marelli, Rino Micheloni
2017	J	`jnl`	Architectural and Integration Options for 3D NAND Flash Memories. Comput. Rino Micheloni, Luca Crippa, Cristian Zambelli, Piero Olivo
2017	J	`jnl`	Array Architectures for 3-D NAND Flash Memories. Proc. IEEE Rino Micheloni, Seiichi Aritome, Luca Crippa
2017	J	`jnl`	Solid-State Drive (SSD): A Nonvolatile Storage System. Proc. IEEE Rino Micheloni
2017	J	`jnl`	Solid-State Drives (SSDs) [Scanning the Issue]. Proc. IEEE Rino Micheloni, Piero Olivo
2017	J	`jnl`	Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance. Proc. IEEE Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Piero Olivo
2016	—	`ch.`	3D Charge Trap NAND Flash Memories. 3D Flash Memories Luca Crippa, Rino Micheloni
2016	—	`book`	3D Flash Memories 3D Flash Memories Rino Micheloni
2016	—	`ch.`	3D Floating Gate NAND Flash Memories. 3D Flash Memories Rino Micheloni, Luca Crippa
2016	—	`ch.`	3D Multi-chip Integration and Packaging Technology for NAND Flash Memories. 3D Flash Memories Herb Huang, Rino Micheloni
2016	—	`ch.`	3D Stacked NAND Flash Memories. 3D Flash Memories Rino Micheloni, Luca Crippa
2016	—	`ch.`	Advanced Architectures for 3D NAND Flash Memories with Vertical Channel. 3D Flash Memories Luca Crippa, Rino Micheloni
2016	—	`ch.`	BCH and LDPC Error Correction Codes for NAND Flash Memories. 3D Flash Memories Alessia Marelli, Rino Micheloni
2015	—	`conf`	Design space exploration of latency and bandwidth in RRAM-based solid state drives. NVMTS Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Stephen Bates, Piero Olivo
2015	J	`jnl`	SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Marco Indaco, Stefano Di Carlo, Paolo Prinetto, Davide Bertozzi, Piero Olivo
2014	J	`jnl`	Overclocking nand Flash Memory I/O Link in LDPC-Based SSDs. IEEE Trans. Circuits Syst. II Express Briefs Kai Zhao, Jiangpeng Li, Jun Ma, Rino Micheloni, Tong Zhang
2014	A	`conf`	SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives. DATE Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Salvatore Galfano, Marco Indaco, Stefano Di Carlo, Paolo Prinetto, Piero Olivo, Davide Bertozzi
2009	J	`jnl`	3-D Data Storage, Power Delivery, and RF/Optical Transceiver - Case Studies of 3-D Integration From System Design Perspectives. Proc. IEEE Tong Zhang, Rino Micheloni, Guoyan Zhang, Zhaoran Rena Huang, James Jian-Qiang Lu
2009	J	`jnl`	Non-Volatile Memories for Removable Media. Proc. IEEE Rino Micheloni, Massimiliano Picca, Stefano Amato, Helmut Schwalm, Michael Scheppler, Stefano Commodaro
2006	—	`conf`	A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput. ISSCC Rino Micheloni, R. Ravasio, Alessia Marelli, E. Alice, V. Altieri, A. Bovino, Luca Crippa, E. Di Martino, L. D'Onofrio, A. Gambardella, E. Grillea, G. Guerra, D. Kim, C. Missiroli, Ilaria Motta, A. Prisco, Giancarlo Ragone, M. Romano, Miriam Sangalli, P. Sauro, Marco Scotti, S. Won
2004	—	`conf`	High input range sense comparator for multilevel Flash memories. ISCAS (2) Alessandro Cabrini, Rino Micheloni, Osama Khouri, Stefano Gregori, Guido Torelli
2003	J	`jnl`	High-voltage management in single-supply CHE NOR-type flash memories. Proc. IEEE Ilaria Motta, Giancarlo Ragone, Osama Khouri, Guido Torelli, Rino Micheloni
2003	J	`jnl`	The flash memory read path: building blocks and critical aspects. Proc. IEEE Rino Micheloni, Luca Crippa, Miriam Sangalli, Giovanni Campardo
2001	—	`conf`	An Error Control Code Scheme for Multilevel Flash Memories. MTDT Stefano Gregori, Guido Torelli, Osama Khouri, Rino Micheloni
2001	—	`conf`	Low Output Resistance Charge Pump for Flash Memory Programming. MTDT Osama Khouri, Stefano Gregori, Dario Soltesz, Guido Torelli, Rino Micheloni
2001	—	`conf`	Stand-by low-power architecture in a 3 V-only 2-bit/cell 64-Mbit flash memory. ICECS Rino Micheloni, Ilaria Motta, Osama Khouri, Guido Torelli
2000	J	`jnl`	40-mm IEEE J. Solid State Circuits Giovanni Campardo, Rino Micheloni, Stefano Commodaro, Emilio Yero, Matteo Zammattio, Sabina Mognoni, Andrea Sacco, Massimiliano Picca, Alessandro Manstretta, Marco Scotti, Ilaria Motta, C. Golla, Andrea Pierin, Roberto Bez, Alessandro Grossi, Alberto Modelli, Angelo Visconti, Osama Khouri, Guido Torelli
2000	—	`conf`	Construction of polyvalent error control codes for multilevel memories. ICECS Stefano Gregori, Pietro Ferrari, Rino Micheloni, Guido Torelli
2000	—	`conf`	Fast Voltage Regulator for Multilevel Flash Memories. MTDT Osama Khouri, Rino Micheloni, Stefano Gregori, Guido Torelli
2000	—	`conf`	Hierarchical Sector Biasing Organization for Flash Memories. MTDT Rino Micheloni, Matteo Zammattio, Giovanni Campardo, Osama Khouri, Guido Torelli
2000	—	`conf`	High-speed low-power sense comparator for multilevel flash memories. ICECS Andrea Pierin, Stefano Gregori, Osama Khouri, Rino Micheloni, Guido Torelli
2000	—	`conf`	Program word-line voltage generator for multilevel flash memories. ICECS Osama Khouri, Rino Micheloni, Andrea Sacco, Giovanni Campardo, Guido Torelli