Rinkle Jain

17 papers C 2Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2024 — conf
28.6 An 87% Efficient 2V-Input, 200A Voltage Regulator Chiplet Enabling Vertical Power Delivery in Multi-kW Systems-on-Package.
ISSCC
Rinkle Jain, Shunjiang Xu, Rajiv Kaushal, Carlos Mariscal, Humberto Caballero, Tamir Salus, Christopher Schaef, Anup Deka, Aruna Payala, Keng Chen, Huong T. Do, Jonathan Douglas
2023 J jnl
A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks.
IEEE J. Solid State Circuits
Renzhi Liu, K. T. Asma Beevi, Richard Dorrance, Timothy F. Cox, Rinkle Jain, Tolga Acikalin, Zhen Zhou, Tae-Young Yang, Johanny Escobar-Pelaez, Shuhei Yamada, Kenneth P. Foust, Brent R. Carlton
2023 J jnl
A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer.
IEEE J. Solid State Circuits
Minxiang Gong, Hua Chen, Xin Zhang, Rinkle Jain, Arijit Raychowdhury
2021 — conf
A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS.
CICC
Hao Luo, Somnath Kundu, Chun C. Lee, Rinkle Jain, Sarah Shahraini, Eduardo Alban, Timo Huusari, Jason Mix, Nasser A. Kurd, Mohamed Abdel-Moneum, Brent R. Carlton
2019 J jnl
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits
Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2018 J jnl
A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS.
IEEE J. Solid State Circuits
Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Pavan Kumar, Rinkle Jain, Sheldon Weng, Stephen T. Kim, George E. Matthew, Nachiket V. Desai, Xiaosen Liu, Krishnan Ravichandran, James W. Tschanz, Vivek De
2018 — conf
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
ISSCC
Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2017 — conf
20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS.
ISSCC
Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Sheldon Weng, Krishnan Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, George E. Matthew, Jim Tschanz, Vivek De
2016 J jnl
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator.
IEEE J. Solid State Circuits
Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2015 — conf
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.
ISSCC
Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
2015 J jnl
Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits
Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, Krishnan Ravichandran, James W. Tschanz, Vivek De
2014 — conf
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep.
ISSCC
Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De
2014 J jnl
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits
Rinkle Jain, Bibiche M. Geuskens, Stephen T. Kim, Muhammad M. Khellah, Jaydeep P. Kulkarni, James W. Tschanz, Vivek De
2014 C conf
A staircase conductance modulation scheme for input-current-shaping in switched-capacitor DC-DC converters.
ISCAS
Sally Safwat, Rinkle Jain, Dawson Kesling
2014 — conf
Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS.
CICC
Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, James W. Tschanz, Krishnan Ravichandran, Vivek De
2011 C conf
A novel control technique to eliminate output-voltage-ripple in switched-capacitor DC-DC converters.
ISCAS
Loai G. Salem, Rinkle Jain
2006 J jnl
A Comprehensive Analysis of Hybrid Phase-Modulated Converter With Current-Doubler Rectifier and Comparison With Its Center-Tapped Counterpart.
IEEE Trans. Ind. Electron.
Rinkle Jain, Ned Mohan, Rajapandian Ayyanar, Robbert M. Button