Rinaldo Castello

118 papers A 1C 12Journal 61Unranked 44

Year	Rank	Type	Title / Venue / Authors
2023	C	`conf`	A 36 GHz Bandwidth, High Linear, Low Power, Driver Modulator, in 28 nm CMOS Technology Based on Quantized-Analog Signal Processing. ISCAS Xhulio Selmani, Gurjeet Singh, Rinaldo Castello, Antonio Liscidini
2023	—	`conf`	A Wide Bandwidth, Low Power, Linear Quantized-Analog VGA in 28 nm CMOS Technology and 1.2V Supply. PRIME Gurjeet Singh, Xhulio Selmani, Rinaldo Castello, Antonio Liscidini
2023	—	`conf`	An Interferer-Tolerant RX with Translational Positive Feedback for 5G NR Applications Achieving 3.4 dB NF and 18 dBm OOB IIP3. ESSCIRC Simone Lecchi, Danilo Manstretta, Rinaldo Castello
2022	J	`jnl`	A 400-μW IoT Low-IF Voltage-Mode Receiver Front-End With Charge-Sharing Complex Filter. IEEE J. Solid State Circuits Jin Jin, Jianhui Wu, Rinaldo Castello, Danilo Manstretta
2022	—	`conf`	A 58 GHz Bandwidth, and less than 1.8% THD, Mach-Zehnder Driver, in 28 nm CMOS Technology. ESSCIRC Nicola Cordioli, Danilo Manstretta, Rinaldo Castello
2022	—	`conf`	An FDD Auxiliary Receiver with a Highly Linear Low Noise Amplifier. ESSCIRC Jin Jin, Simone Lecchi, Rinaldo Castello, Danilo Manstretta
2022	—	`conf`	Filtering Trans-Impedance Amplifiers: from mW of Power to GHz of Bandwidth. CICC Nimesh Nadishka Miral, Karan Sohal, Danilo Manstretta, Rinaldo Castello
2022	—	`conf`	Reminiscing through 40 years of CMOS analog circuit design: from audio to GHz. ESSCIRC Rinaldo Castello
2021	—	`conf`	A 17 mW 33 dBm IB-OIP3 0.5-1.5 GHz Bandwidth TIA Based on an Inductor-Stabilized OTA. ESSCIRC Nimesh Nadishka Miral, Danilo Manstretta, Rinaldo Castello
2021	C	`conf`	A 2 ISCAS Karan Sohal, Danilo Manstretta, Rinaldo Castello
2021	—	`conf`	A 400-µW Low-IF IoT Receiver Front-End with Tunable Charge-Sharing Complex Filter. ESSCIRC Jin Jin, Jianhui Wu, Rinaldo Castello, Danilo Manstretta
2021	J	`jnl`	A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture. IEEE Trans. Very Large Scale Integr. Syst. Mohsen Javadi, Hossein Miar Naimi, Saheed Tijani, Danilo Manstretta, Rinaldo Castello
2020	J	`jnl`	Analysis and Design of a 260-MHz RF Bandwidth +22-dBm OOB-IIP3 Mixer-First Receiver With Third-Order Current-Mode Filtering TIA. IEEE J. Solid State Circuits Giacomo Pini, Danilo Manstretta, Rinaldo Castello
2019	J	`jnl`	A 1.5-2.8 GHz current-mode LNTA achieving >25 dBm IIP3 and +8 dBm P-1dB gain compression. Microelectron. J. Ehsan Kargaran, Danilo Manstretta, Rinaldo Castello
2019	—	`conf`	A 150-MHz TIA with un-Conventional OTA Stabilization Technique via Local Active Feed-Back. PRIME Mohammadmehdi Deilam Salehi, Danilo Manstretta, Rinaldo Castello
2019	—	`conf`	A 260-MHz RF Bandwidth Mixer-First Receiver With Third-Order Current-Mode Filtering TIA. ESSCIRC Giacomo Pini, Danilo Manstretta, Rinaldo Castello
2019	—	`conf`	A Sub-0.6V, 330 µW, 0.15 mm A-SSCC Ehsan Kargaran, Carl Bryant, Danilo Manstretta, Jon Strange, Rinaldo Castello
2019	—	`conf`	A Wideband Saw-Less Transmitter Operating in Closed-Loop With Embedded N-Path Filtering. CICC Arianna Coccia, Danilo Manstretta, Rinaldo Castello, Luca Fanori
2018	—	`conf`	A Mixer-1st Auxiliary Receiver for Full-Duplex Self-Interference Cancellation. NGCAS D. Prevcdelli, Giacomo Pini, Danilo Manstretta, Rinaldo Castello
2018	C	`conf`	A Sub-1V, 220 μW Receiver Frontend for Wearable Wireless Sensor Network Applications. ISCAS Ehsan Kargaran, Danilo Manstretta, Rinaldo Castello
2018	—	`conf`	A Sub-IV, 72 μW Stacked LNA-VCO for Wireless Sensor Network Applications. PRIME Ehsan Kargaran, Danilo Manstretta, Rinaldo Castello
2018	J	`jnl`	A TVWS receiver with balanced output self-calibrated IIP2 LNTA employing a low-noise current multiplier. Integr. Arianna Coccia, Saheed Tijani, Danilo Manstretta, Rinaldo Castello
2018	J	`jnl`	An FDD Wireless Diversity Receiver With Transmitter Leakage Cancellation in Transmit and Receive Bands. IEEE J. Solid State Circuits Daniele Montanari, Gerardo Castellano, Ehsan Kargaran, Giacomo Pini, Saheed Tijani, Davide De Caro, Antonio Giuseppe Maria Strollo, Danilo Manstretta, Rinaldo Castello
2018	J	`jnl`	Analysis and Design of a 20-MHz Bandwidth, 50.5-dBm OOB-IIP3, and 5.4-mW TIA for SAW-Less Receivers. IEEE J. Solid State Circuits Giacomo Pini, Danilo Manstretta, Rinaldo Castello
2018	J	`jnl`	Design and Analysis of 2.4 GHz 30~µW CMOS LNAs for Wearable WSN Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Ehsan Kargaran, Danilo Manstretta, Rinaldo Castello
2017	—	`conf`	A 0.7-2 GHz auxiliary receiver with enhanced compression for SAW-less FDD. ESSCIRC Danilo Montanari, Danilo Manstretta, Rinaldo Castello, Gerardo Castellano
2017	C	`conf`	A 30μW, 3.3dB NF CMOS LNA for wearable WSN applications. ISCAS Ehsan Kargaran, Danilo Manstretta, Rinaldo Castello
2017	J	`jnl`	A SAW-Less 2.4-GHz Receiver Front-End With 2.4-mA Battery Current for SoC Coexistence. IEEE J. Solid State Circuits Matteo Ramella, Ivan Fabiano, Danilo Manstretta, Rinaldo Castello
2016	—	`conf`	Highly linear TIA for SAW-less FDD receivers. A-SSCC Giacomo Pini, Danilo Manstretta, Rinaldo Castello
2015	—	`conf`	A 1.7-2.1GHz +23dBm TX power compatible blocker tolerant FDD receiver with integrated duplexer in 28nm CMOS. A-SSCC Matteo Ramella, Ivan Fabiano, Danilo Manstretta, Rinaldo Castello
2015	—	`conf`	A 2.4GHz low-power SAW-less receiver for SoC coexistence. A-SSCC Matteo Ramella, Ivan Fabiano, Danilo Manstretta, Rinaldo Castello
2015	J	`jnl`	Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering. IEEE J. Solid State Circuits Marco Garampazzi, Paulo M. Mendes, Nicola Codega, Danilo Manstretta, Rinaldo Castello
2014	—	`conf`	A 195.6dBc/Hz peak FoM P-N class-B oscillator with transformer-based tail filtering. ESSCIRC Marco Garampazzi, Paulo M. Mendes, Nicola Codega, Danilo Manstretta, Rinaldo Castello
2014	J	`jnl`	A Current-Mode, Low Out-of-Band Noise LTE Transmitter With a Class-A/B Power Mixer. IEEE J. Solid State Circuits Nicola Codega, Paolo Rossi, Alberto Pirola, Antonio Liscidini, Rinaldo Castello
2014	J	`jnl`	A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers. IEEE J. Solid State Circuits Antonio Liscidini, Luca Fanori, Pietro Andreani, Rinaldo Castello
2014	—	`conf`	A low power/noise emission LTE fully class A/B transmitter with a programmable output balun. ICECS Elisa Girard, Nicola Codega, Rinaldo Castello
2014	—	`conf`	A multi-band Rel9 WCDMA/HSDPA/TDD LTE and FDD LTE transceiver with envelope tracking. ESSCIRC Shahrzad Tadjpour, Paolo Rossi, Luca Romanò, Ramesh Chokkalingam, Hamid Firouzkouhi, Feng Shi, M. Leroux, Danilo Gerna, A. Venca, John Vasa, Bala Ramachandran, Brian Brunn, Alberto Pirola, Daniele Ottini, A. Milani, Enrico Sacchi, M. Behera, X. Chen, U. Decanis, Marika Tedeschi, S. DalToso, W. Eyssa, C. Cakir, C. Prakash, Yong He, Nader Damavandi, R. Srinivasan, Dan Shum, X. Fan, C. Yu, Engin Pehlivanoglu, Hossein Zarei, Aravind Loke, Gregory Uehara, Rinaldo Castello, Y. Song
2014	J	`jnl`	An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators. IEEE J. Solid State Circuits Marco Garampazzi, Stefano Dal Toso, Antonio Liscidini, Danilo Manstretta, P. Mendez, Luca Romanò, Rinaldo Castello
2013	J	`jnl`	A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS. IEEE J. Solid State Circuits Jody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Samuel Er-Shen Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello
2013	—	`conf`	A low out-of-band noise LTE transmitter with current-mode approach. ESSCIRC Nicola Codega, Antonio Liscidini, Rinaldo Castello
2013	J	`jnl`	An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory. IEEE Trans. Circuits Syst. II Express Briefs Marco Sosio, Antonio Liscidini, Rinaldo Castello
2013	—	`conf`	An LTE transmitter using a class-A/B power mixer. ISSCC Paolo Rossi, Nicola Codega, Danilo Gerna, Antonio Liscidini, Daniele Ottini, Yong He, Alberto Pirola, Enrico Sacchi, Gregory Uehara, Chao Yang, Rinaldo Castello
2013	J	`jnl`	SAW-Less Analog Front-End Receivers for TDD and FDD. IEEE J. Solid State Circuits Ivan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello
2013	—	`conf`	SAW-less analog front-end receivers for TDD and FDD. ISSCC Ivan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello
2012	J	`jnl`	A 2G/3G Cellular Analog Baseband Based on a Filtering ADC. IEEE Trans. Circuits Syst. II Express Briefs Marco Sosio, Antonio Liscidini, Rinaldo Castello
2012	—	`conf`	A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers. ISSCC Antonio Liscidini, Luca Fanori, Pietro Andreani, Rinaldo Castello
2012	—	`conf`	A 40MHz-to-1GHz fully integrated multistandard silicon tuner in 80nm CMOS. ISSCC Jody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Sam Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello
2012	J	`jnl`	A Dither-Less All Digital PLL for Cellular Transmitters. IEEE J. Solid State Circuits Luca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini, Rinaldo Castello
2011	—	`conf`	A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC. ESSCIRC Marco Sosio, Antonio Liscidini, Rinaldo Castello, Fernando De Bernardinis
2011	—	`conf`	A dither-less all digital PLL for cellular transmitters. CICC Luca Vercesi, Luca Fanori, Fernando De Bernardinis, Antonio Liscidini, Rinaldo Castello
2011	J	`jnl`	Corrections to "Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping" [Sep 10 1770-1780]. IEEE J. Solid State Circuits Alberto Pirola, Antonio Liscidini, Rinaldo Castello
2010	—	`conf`	3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL. ISSCC Luca Fanori, Antonio Liscidini, Rinaldo Castello
2010	J	`jnl`	A Class-G Headphone Amplifier in 65 nm CMOS Technology. IEEE J. Solid State Circuits Alex Lollio, Giacomino Bollati, Rinaldo Castello
2010	J	`jnl`	Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning. IEEE J. Solid State Circuits Luca Fanori, Antonio Liscidini, Rinaldo Castello
2010	—	`conf`	Class-G headphone driver in 65nm CMOS technology. ISSCC Alex Lollio, Giacomino Bollati, Rinaldo Castello
2010	J	`jnl`	Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping. IEEE J. Solid State Circuits Alberto Pirola, Antonio Liscidini, Rinaldo Castello
2010	J	`jnl`	Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications. IEEE J. Solid State Circuits Marika Tedeschi, Antonio Liscidini, Rinaldo Castello
2010	J	`jnl`	Two-Dimensions Vernier Time-to-Digital Converter. IEEE J. Solid State Circuits Luca Vercesi, Antonio Liscidini, Rinaldo Castello
2009	—	`conf`	A 1.25mW 75dB-SFDR CT filter with in-band noise reduction. ISSCC Antonio Liscidini, Alberto Pirola, Rinaldo Castello
2009	—	`conf`	A VDSL2 CPE AFE in 0.15µm CMOS with integrated line driver. ISSCC Giovanni Cesura, Alessandro Bosi, Francesco Rezzi, Rinaldo Castello, Jenkin Chan, SaiBun Wong, Chi Fan Yung, Ovidiu Carnu, Thomas Cho
2009	—	`conf`	Time to digital converter based on a 2-dimensions Vernier architecture. CICC Antonio Liscidini, Luca Vercesi, Rinaldo Castello
2008	—	`conf`	A 0.23mm2 free coil ZigBee receiver based on a bond-wire self-oscillating mixer. ESSCIRC Marika Tedeschi, Antonio Liscidini, Rinaldo Castello
2008	—	`conf`	A 2.4 GHz 3.6mW 0.35mm ISSCC Antonio Liscidini, Marika Tedeschi, Rinaldo Castello
2008	J	`jnl`	A Reconfigurable Narrow-Band MB-OFDM UWB Receiver Architecture. IEEE Trans. Circuits Syst. II Express Briefs Danilo Manstretta, Nicola Laurenti, Rinaldo Castello
2008	J	`jnl`	Analysis and Design of Configurable LNAs in Feedback Common-Gate Topologies. IEEE Trans. Circuits Syst. II Express Briefs Antonio Liscidini, Giuseppe Martini, Daniele Mastantuono, Rinaldo Castello
2006	J	`jnl`	A 0.13 μm CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier. IEEE J. Solid State Circuits Antonio Liscidini, Massimo Brandolini, Davide Sanzogni, Rinaldo Castello
2006	—	`conf`	A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO. ISSCC Antonio Liscidini, Andrea Mazzanti, Riccardo Tonietto, Luca Vandi, Pietro Andreani, Rinaldo Castello
2006	J	`jnl`	A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC. IEEE Trans. Circuits Syst. II Express Briefs Roberto G. Massolini, Giovanni Cesura, Rinaldo Castello
2006	—	`conf`	Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End. CICC Antonio Liscidini, Cesare Ghezzi, Emanuele Depaoli, Guido Albasini, Ivan Bietti, Rinaldo Castello
2006	J	`jnl`	Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell. IEEE J. Solid State Circuits Antonio Liscidini, Andrea Mazzanti, Riccardo Tonietto, Luca Vandi, Pietro Andreani, Rinaldo Castello
2005	J	`jnl`	A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner. IEEE J. Solid State Circuits Mario Valla, Giampiero Montagna, Rinaldo Castello, Riccardo Tonietto, Ivan Bietti
2004	J	`jnl`	A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications. IEEE J. Solid State Circuits Enrico Temporiti, Guido Albasini, Ivan Bietti, Rinaldo Castello, Matteo Colombo
2003	—	`conf`	A 15 mW, 70 kHz 1/f corner direct conversion CMOS receiver. CICC Enrico Sacchi, Ivan Bietti, Simone Erbat, Luns Tee, Paolo Vilmercati, Rinaldo Castello
2003	J	`jnl`	A 35-mW 3.6-mm2 fully integrated 0.18-μm CMOS GPS radio. IEEE J. Solid State Circuits Giampiero Montagna, Giuseppe Gramegna, Ivan Bietti, Massimo Franciotta, Andrea Baschirotto, Placido De Vita, Roberto Pelleriti, Mario Paparo, Rinaldo Castello
2003	—	`conf`	An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques. CICC Ivan Bietti, Enrico Temporiti, Guido Albasini, Rinaldo Castello
2001	J	`jnl`	A 2-dB noise figure 900-MHz differential CMOS LNA. IEEE J. Solid State Circuits Francesco Gatta, Enrico Sacchi, Francesco Svelto, Paolo Vilmercati, Rinaldo Castello
2001	J	`jnl`	An eighth-order CMOS low-pass filter with 30-120 MHz tuning range and programmable boost. IEEE J. Solid State Circuits Giacomino Bollati, Stefano Marchese, Marco Demicheli, Rinaldo Castello
2001	J	`jnl`	Implementation of a CMOS LNA plus mixer for GPS applications with no external components. IEEE Trans. Very Large Scale Integr. Syst. Francesco Svelto, Stefano Deantoni, Giampiero Montagna, Rinaldo Castello
2000	C	`conf`	A 1 V 1.2 μW 4th order bandpass switched-opamp SC filter for a cardiac pacer sensing stage. ISCAS Andrea Baschirotto, Domenico Bijno, Rinaldo Castello, Federico Montecchi
2000	—	`conf`	A 1 mA, -120.5 dbc/Hz at 600 kHz from 1.9 GHz fully tuneable LC CMOS VCO. CICC Francesco Svelto, Stefano Deantoni, Rinaldo Castello
2000	J	`jnl`	A 1.3 GHz low-phase noise fully tunable CMOS LC VCO. IEEE J. Solid State Circuits Francesco Svelto, Stefano Deantoni, Rinaldo Castello
2000	J	`jnl`	A 200-Ms/s 10-mW switched-capacitor filter in 0.5-μm CMOS technology. IEEE J. Solid State Circuits Andrea Baschirotto, F. Severi, Rinaldo Castello
2000	—	`conf`	A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi. CICC Giacomino Bollati, Angelo Dati, Giorgio Betti, Ivan Bietti, Francesco Brianti, Melchiorre Bruccoleri, M. Coltella, P. Demartini, Marco Demicheli, Paolo Gadducci, Stefano Marchese, Daniele Ottini, Valerio Pisati, Francesco Rezzi, A. Rossi, P. Savo, C. Tonci, Rinaldo Castello
2000	A	`conf`	An 8mA, 3.8dB NF, 40dB gain CMOS front-end for GPS applications. ISLPED Francesco Svelto, Stefano Deantoni, Giampiero Montagna, Rinaldo Castello
2000	C	`conf`	High-frequency CMOS low-power single-branch continuous-time filters. ISCAS Andrea Baschirotto, Ugo Baschirotto, Rinaldo Castello
2000	C	`conf`	Solutions for image rejection CMOS LNA. ISCAS Francesco Svelto, Giampiero Montagna, Stefano Deantoni, Giulio Braschi, Rinaldo Castello
1999	—	`conf`	A 1.3 GHz CMOS VCO with 28% frequency tuning. CICC Francesco Svelto, Stefano Deantoni, Rinaldo Castello
1999	—	`conf`	A 450 Mbit/s EPR4 PRML read/write channel. CICC Marco Demicheli, Giacomino Bollati, Paolo Gadducci, L. Affortunati, Roberto Alini, G. Betti, I. Bietti, F. Brianti, Melchiorre Bruccoleri, M. Coltella, P. Demartini, Stefano Marchese, D. Ottini, Valerio Pisati, Salvatore Portaluri, A. Rossi, P. Savo, C. Tonci, Rinaldo Castello
1999	J	`jnl`	A low-voltage topology for CMOS RF mixers. IEEE Trans. Consumer Electron. Francesco Svelto, Matteo Conta, Valentina Della Torre, Rinaldo Castello
1998	J	`jnl`	A versatile high-speed bipolar charge-sensitive preamplifier for calorimeter applications. IEEE J. Solid State Circuits Andrea Baschirotto, Rinaldo Castello, Gianluigi Ezio Pessina, Pier Giorgio Rancoita, A. Seidman
1998	J	`jnl`	Measurement and modeling of Si integrated inductors. IEEE Trans. Instrum. Meas. Paolo Arcioni, Rinaldo Castello, Giuseppe De Astis, Enrico Sacchi, Francesco Svelto
1997	J	`jnl`	A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing. IEEE J. Solid State Circuits Andrea Baschirotto, Rinaldo Castello
1997	J	`jnl`	A 10.7-MHz BiCMOS high-Q double-sampled SC bandpass filter. IEEE J. Solid State Circuits Angelo Nagari, Andrea Baschirotto, Federico Montecchi, Rinaldo Castello
1997	J	`jnl`	A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier. IEEE J. Solid State Circuits Massimo Franciotta, G. Colli, Rinaldo Castello
1997	J	`jnl`	A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo. IEEE J. Solid State Circuits Roberto Alini, Giorgio Betti, Ivan Bietti, Giacomino Bollati, Francesco Brianti, Angelo Dati, Marco Demicheli, Paolo Gadducci, Stefano Marchese, Emanuele Marconetti, Valerio Pisati, Maurizio Zuffada, Rinaldo Castello, Fereidoon Heydari, Peter Gillen, Gerry Maguire, Marcus Marrow, Stephen McDonagh, Fergus O'Brien, Jerry O'Brien, Niall O'hEarcain, Deirdre Reddy, Lisa Fredrickson, Dennis Stone, LeRoy Volz
1997	J	`jnl`	A 3-V 5.4-mW BiCMOS track & hold circuit with sampling frequency up to 150 MHz. IEEE J. Solid State Circuits Luca Schillaci, Andrea Baschirotto, Rinaldo Castello
1997	J	`jnl`	A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization. IEEE J. Solid State Circuits Francesco Rezzi, Ivan Bietti, Marco Cazzaniga, Rinaldo Castello
1996	J	`jnl`	A PLL-based frequency synthesizer for 160-MHz double-sampled SC filters. IEEE J. Solid State Circuits Francesco Rezzi, Federico Montecchi, Rinaldo Castello
1996	—	`conf`	A readout channel with 1 nF fully integrated capacitor for AMS space experiment. ICECS Andrea Baschirotto, G. Boella, Rinaldo Castello, Gianluigi Ezio Pessina, Pier Giorgio Rancoita
1995	J	`jnl`	A 15 MHz 20 mW BiCMOS switched-capacitor biquad operating with 150 Ms/s sampling frequency. IEEE J. Solid State Circuits Andrea Baschirotto, Federico Montecchi, Rinaldo Castello
1995	J	`jnl`	A single-chip 9-32 mb/s read/write channel for disk-drive applications. IEEE J. Solid State Circuits Maurizio Zuffada, Roberto Alini, Paolo Colletti, Marco Demicheli, Marco Gregori, David Moloney, Salvatore Portaluri, Fabrizio Sacchi, Sadik O. Arf, Vincent Condito, Rinaldo Castello
1994	C	`conf`	Design of High-Frequency BiCMOS Continuous-Time Filters with Low-Output Impedance Transconductor. ISCAS Andrea Baschirotto, Francesco Rezzi, Roberto Alini, Rinaldo Castello
1994	C	`conf`	High Speed Monolithic Read-Out System for High Energy Physics Experiments. ISCAS Andrea Baschirotto, M. Bosetti, Rinaldo Castello, Alberto Gola, Gianluigi Ezio Pessina, Pier Giorgio Rancoita, M. Rattaggi, M. Redaelli, G. Terzi
1993	J	`jnl`	A BiCMOS speech circuit with only two external components. IEEE J. Solid State Circuits Rinaldo Castello, Luciano Tomasini
1993	J	`jnl`	A CMOS low-distortion fully differential power amplifier with double nested Miller compensation. IEEE J. Solid State Circuits Sergio Pernici, Germano Nicollini, Rinaldo Castello
1993	C	`conf`	Exact Design of High-frequency SC Circuits with Low-gain Op Amps. ISCAS Andrea Baschirotto, Rinaldo Castello, Federico Montecchi
1993	C	`conf`	High-speed BiCMOS Operational Amplifier for Switched-capacitor Circuits. ISCAS Andrea Baschirotto, Roberto Alini, Rinaldo Castello, Federico Montecchi
1993	C	`conf`	Novel Linearizaiton Circuit for BiCMOS Transconductors Used in High Frequency OTA-C Filters. ISCAS Francesco Rezzi, Valerio Pisati, Rinaldo Castello, Roberto Alini
1992	J	`jnl`	100-V high-performance amplifiers in BCD technology for SLIC applications. IEEE J. Solid State Circuits Rinaldo Castello, Ferdinando Lari, Marco Siligoni, Luciano Tomasini
1992	J	`jnl`	Tunable BiCMOS continuous-time filter for high-frequency applications. IEEE J. Solid State Circuits Roberto Alini, Andrea Baschirotto, Rinaldo Castello
1992	J	`jnl`	Zero placement technique for iir switched capacitor anti-aliasing decimators. Int. J. Circuit Theory Appl. Andrea Baschirotto, Rinaldo Castello, Federico Montecchi
1991	J	`jnl`	1.5-V high-performance SC filters in BiCMOS technology. IEEE J. Solid State Circuits Rinaldo Castello, Luciano Tomasini
1991	J	`jnl`	A high-linearity 50- Omega CMOS differential driver for ISDN applications. IEEE J. Solid State Circuits Rinaldo Castello, Germano Nicollini, Pierluca Monguzzi
1990	J	`jnl`	A 500-nA sixth-order bandpass SC filter. IEEE J. Solid State Circuits Rinaldo Castello, Alberto G. Grassi, Stefano Donati
1990	J	`jnl`	A fully differential CMOS line driver for ISDN. IEEE J. Solid State Circuits Liciano Tomasini, Alberto Gola, Rinaldo Castello
1990	J	`jnl`	Analog front end of an ECBM transceiver for ISDN. IEEE J. Solid State Circuits Rinaldo Castello, Luciano Tomasini, Sergio Pernici, Franco Salerno, Michelangelo Mazzucco, Marco Ferro
1989	J	`jnl`	A floating CMOS bandgap voltage reference for differential applications. IEEE J. Solid State Circuits Marco Ferro, Franco Salerno, Rinaldo Castello
1989	J	`jnl`	A scalable switched-capacitor filter implemented in 1.25- mu m technology. IEEE J. Solid State Circuits Sui-Ping Shieh, Chorng-Kuang Wang, Rinaldo Castello, Paul R. Gray