Rimon Ikeno

16 papers A 1B 1Journal 6Unranked 8
YearRankTypeTitle / Venue / Authors
2025 — conf
6.4 A 400×400 3.24µm 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor.
ISSCC
Tsung-Hsun Tsai, Kwuang-Han Chang, Andrew Berkovich, Raffaele Capoccia, Song Chen, Zhao Wang, Chiao Liu, Yi-Hsuan Lin, Sheng-Yeh Lai, Hao-Ming Hsu, Hirofumi Abe, Kazuya Mori, Hideyuki Fukuhara, Chih-Hao Lin, Toshiyuki Isozaki, Wei-Chen Li, Wei-Fan Chou, Masayuki Uno, Rimon Ikeno, Masato Nagamatsu, Guang Yang, Shou-Gwo Wuu, Lyle Bainbridge
2025 J jnl
A 3.96-μm, 124-dB Dynamic-Range, Digital-Pixel Sensor With Triple- and Single-Quantization Operations for Monochrome and Near-Infrared Dual-Channel Global Shutter Operation.
IEEE J. Solid State Circuits
Ken Miyauchi, Masayuki Uno, Toshiyuki Isozaki, Hideyuki Fukuhara, Kazuya Mori, Hirofumi Abe, Masato Nagamatsu, Rimon Ikeno, Isao Takayanagi, Hsin-Li Chen, Chih-Hao Lin, Wen-Chien Fu, Shou-Gwo Wuu, Song Chen, Lyle Bainbridge, Qing Chao, Ramakrishna Chilukuri, Wei Gao, Andrew P. Hammond, Tsung-Hsun Tsai, Chiao Liu
2023 — conf
A 3.96μm, 124dB Dynamic Range, 6.2mW Stacked Digital Pixel Sensor with Monochrome and Near-Infrared Dual-Channel Global Shutter Capture.
VLSI Technology and Circuits
Song Chen, Chiao Liu, Lyle Bainbridge, Qing Chao, Ramakrishna Chilukuri, Wei Gao, Andrew P. Hammond, Tsung-Hsun Tsai, Ken Miyauchi, Isao Takayanagi, Masato Nagamatsu, Hirofumi Abe, Kazuya Mori, Masayuki Uno, Toshiyuki Isozaki, Rimon Ikeno, Hsin-Li Chen, Chih-Hao Lin, Wen-Chien Fu, Shou-Gwo Wuu
2023 J jnl
Analysis of Light Intensity and Charge Holding Time Dependence of Pinned Photodiode Full Well Capacity.
Sensors
Ken Miyauchi, Toshiyuki Isozaki, Rimon Ikeno, Junichi Nakamura
2018 — conf
A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture.
MWSCAS
Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
2018 J jnl
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment.
J. Electron. Test.
Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2017 B conf
Extension of power supply impedance emulation method on ATE for multiple power domain.
ETS
Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2016 — conf
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration.
ICECS
Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada
2016 A conf
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board.
ITC
Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada
2015 — conf
A Technique for Analyzing On-Chip Power Supply Impedance.
ATS
Masahiro Ishida, Toru Nakura, Akira Matsukawa, Rimon Ikeno, Kunihiro Asada
2014 J jnl
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2013 — conf
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection.
ISPD
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2013 J jnl
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada
2013 — conf
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design.
ASP-DAC
Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada
2011 — conf
COOL interconnect low power interconnection technology for scalable 3D LSI design.
COOL Chips
Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto, Fumito Imura, Motohiro Suzuki, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi
1998 J jnl
One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects.
VLSI Design
Rimon Ikeno, Hiroshi Ito, Kunihiro Asada