Riichiro Takemura

20 papers A 1C 1Journal 11Unranked 7
YearRankTypeTitle / Venue / Authors
2012 J jnl
0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs.
IEICE Trans. Electron.
Akira Kotabe, Kiyoo Itoh, Riichiro Takemura
2012 J jnl
A Low-
IEICE Trans. Electron.
Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh
2012 J jnl
Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device.
IEICE Trans. Electron.
Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
2012 C conf
Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device.
ISCAS
Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
2012 J jnl
Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays.
IEICE Trans. Electron.
Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh
2012 J jnl
Spin-transfer torque RAM technology: Review and prospect.
Microelectron. Reliab.
Takayuki Kawahara, Kenchi Ito, Riichiro Takemura, Hideo Ohno
2011 — conf
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs.
CICC
Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi
2010 J jnl
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme.
IEEE J. Solid State Circuits
Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno
2009 — conf
Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays.
ISSCC
Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh
2008 J jnl
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read.
IEEE J. Solid State Circuits
Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno
2007 — conf
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read.
ISSCC
Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno
2007 J jnl
Long-Retention-Time, High-Speed DRAM Array with 12-
IEICE Trans. Electron.
Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara
2007 — conf
Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs.
ICECS
Kiyoo Itoh, Riichiro Takemura
2007 — conf
SPRAM (SPin-transfer torque RAM) design and its impact on digital systems.
ICECS
Takayuki Kawahara, Riichiro Takemura, Hiromasa Takahashi, Hideo Ohno
2006 A conf
A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-V
ISLPED
Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi
2006 J jnl
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM.
IEEE J. Solid State Circuits
Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara
2005 J jnl
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router.
IEEE J. Solid State Circuits
Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara
2005 — conf
A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup.
ICC
Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara
2005 — conf
Phase change RAM operated with 1.5-V CMOS as low cost embedded memory.
CICC
Kenichi Osada, Takayuki Kawahara, Riichiro Takemura, Naoki Kitai, Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi, Hiroshi Moriya, Masahiro Moniwa
2001 J jnl
A multigigabit DRAM technology with 6F
IEEE J. Solid State Circuits
Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh