Richard Ruzicka

37 papers C 17Journal 1Unranked 19
YearRankTypeTitle / Venue / Authors
2023 C conf
Polymorphic RTL Computational Elements.
DSD
Richard Ruzicka, Václav Simek, Jan Nevoral
2022 C conf
Technology Mapping for PAIG Optimised Polymorphic Circuits.
DSD
Richard Ruzicka, Václav Simek
2020 C conf
KL-cuts influence on optimization of polymorphic circuits based on PAIG rewriting.
DDECS
Adam Crha, Václav Simek, Richard Ruzicka
2020 C conf
Power Consumption Analysis of New Generation of Polymorphic Gates.
DDECS
Jan Nevoral, Václav Simek, Richard Ruzicka
2019 C conf
PAIG Rewriting: The Way to Scalable Multifunctional Digital Circuits Synthesis.
DSD
Adam Crha, Václav Simek, Richard Ruzicka
2019 C conf
PoLibSi: Path Towards Intrinsically Reconfigurable Components.
DSD
Jan Nevoral, Václav Simek, Richard Ruzicka
2018 — conf
CMOS Gates with Second Function.
ISVLSI
Jan Nevoral, Richard Ruzicka, Václav Simek
2018 — conf
Efficient Implementation of Bi-Functional RTL Components - Case Study.
NGCAS
Jan Nevoral, Richard Ruzicka
2018 C conf
From Ambipolarity to Multifunctionality: Novel Library of Polymorphic Gates Using Double-Gate FETs.
DSD
Jan Nevoral, Richard Ruzicka, Václav Simek
2018 — conf
Towards novel format for representation of polymorphic circuits.
DTIS
Adam Crha, Václav Simek, Richard Ruzicka
2017 — conf
Compact library of efficient polymorphic gates based on ambipolar transistors.
DTIS
Jan Nevoral, Václav Simek, Richard Ruzicka
2017 — conf
Synthesis tool for design of complex polymorphic circuits.
DTIS
Adam Crha, Richard Ruzicka, Václav Simek
2016 — conf
Evolutionary design of polymorphic gates using ambipolar transistors.
SSCI
Jan Nevoral, Richard Ruzicka, Vojtech Mrazek
2016 — conf
Lets move polymorphism downwards: On the multifunctional logic based on ambipolar behaviour of semiconductor devices.
DTIS
Richard Ruzicka, Radek Tesar
2016 — conf
Modelling and physical implementation of ambipolar components based on organic materials.
ICM
Václav Simek, Radek Tesar, Richard Ruzicka, Adam Crha
2015 — conf
Synthesis Methodology of Polymorphic Circuits Using Polymorphic NAND/NOR Gates.
UKSim
Adam Crha, Richard Ruzicka, Václav Simek
2015 — conf
Toward efficient synthesis method of multifunctional logic circuits.
ICM
Václav Simek, Richard Ruzicka, Adam Crha
2014 — conf
Implementation of a Cellular Automaton with Globally Switchable Rules.
ACRI
Václav Simek, Richard Ruzicka, Adam Crha, Radek Tesar
2014 — conf
Reconfigurable Platform with Polymorphic Digital Gates and Partial Reconfiguration Feature.
EMS
Václav Simek, Richard Ruzicka
2014 — conf
Resistant Gates for Polymorphic Electronics.
EMS
Radek Tesar, Richard Ruzicka, Václav Simek
2013 C ed.
16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013
DDECS
Lukás Sekanina, Görschwin Fey, Jaan Raik, Snorre Aunet, Richard Ruzicka
2013 J jnl
Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit.
Inf. Technol. Control.
Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Václav Simek, Petr Hanácek
2012 C conf
NAND/NOR gate polymorphism in low temperature environment.
DDECS
Richard Ruzicka, Václav Simek
2011 C conf
Behavior of CMOS polymorphic circuits in high temperature environment.
DDECS
Richard Ruzicka, Václav Simek, Lukás Sekanina
2011 C conf
Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles.
DSD
Richard Ruzicka, Václav Simek
2010 C conf
Gracefully Degrading Circuit Controllers Based on Polytronics.
DSD
Richard Ruzicka
2010 C conf
On analysis of fabricated polymorphic circuits.
DDECS
Václav Simek, Richard Ruzicka, Lukás Sekanina
2009 C conf
Dependable Controller Design Using Polymorphic Counters.
DSD
Richard Ruzicka
2009 — conf
Polymorphic FIR Filters with Backup Mode Enabling Power Savings.
AHS
Lukás Sekanina, Richard Ruzicka, Zbysek Gajda
2009 — conf
REPOMO32 - New reconfigurable polymorphic integrated circuit for adaptive hardware.
WEAH
Lukás Sekanina, Richard Ruzicka, Zdenek Vasícek, Roman Prokop, Lukás Fujcik
2008 C conf
Physical Demonstration of Polymorphic Self-Checking Circuits.
IOLTS
Richard Ruzicka, Lukás Sekanina, Roman Prokop
2007 C conf
Test Controller Synthesis Constrained by Circuit Testability Analysis.
DSD
Richard Ruzicka, Josef Strnadel
2006 — conf
Evolutionary circuit design in REPOMO - reconfigurable polymorphic module.
Computational Intelligence
Richard Ruzicka, Lukás Sekanina
2004 — conf
Formal Approach to Synthesis of a Test Controller.
ECBS
Richard Ruzicka, Pavel Tupec
2003 — conf
Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers.
Evolvable Hardware
Lukás Sekanina, Richard Ruzicka
2003 C conf
Testable Design Verification Using Petri Nets.
DSD
Richard Ruzicka
2000 — conf
Formal Approach to the RTL Testability Analysis.
LATW
Zdenek Kotásek, Richard Ruzicka, Jan Hlavicka