Richard Panek

15 papers C 7Unranked 8
YearRankTypeTitle / Venue / Authors
2023 — conf
The Fault-tolerant Single-FPGA Systems with a Self-repair Reconfiguration Controller.
LASCAS
Richard Panek, Jakub Lojda
2021 C conf
Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs.
DSD
Jakub Lojda, Richard Panek, Zdenek Kotásek
2021 — conf
Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery.
EWDTS
Jakub Lojda, Richard Panek, Zdenek Kotásek
2021 C conf
Reliability Analysis of the FPGA Control System with Reconfiguration Hardening.
DSD
Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2021 — conf
Testing Embedded Software Through Fault Injection: Case Study on Smart Lock.
LATS
Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020 — conf
Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock.
EWDTS
Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020 C conf
Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem.
DDECS
Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Martin Krcma, Zdenek Kotásek
2020 — conf
Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks.
LASCAS
Jakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020 C conf
Hardening of Smart Electronic Lock Software against Random and Deliberate Faults.
DSD
Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
2020 — conf
Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study.
VLSI-DAT
Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2019 C conf
Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards.
DSD
Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek
2018 C conf
FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation.
DSD
Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek
2018 — conf
Input and Output Generation for the Verification of ALU: A Use Case.
EWDTS
Ondrej Cekan, Richard Panek, Zdenek Kotásek
2018 — conf
Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation.
EWDTS
Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
2017 C conf
Reliability Analysis and Improvement of FPGA-Based Robot Controller.
DSD
Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek