Richard J. Eickemeyer

21 papers A* 7Journal 12Unranked 1
YearRankTypeTitle / Venue / Authors
2021 A* conf
Energy Efficiency Boost in the AI-Infused POWER10 Processor.
ISCA
Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose
2015 J jnl
Disaggregated and optically interconnected memory: when will it be cost effective?
CoRR
Bülent Abali, Richard J. Eickemeyer, Hubertus Franke, Chung-Sheng Li, Marc Taubenblatt
2015 J jnl
IBM POWER8 performance and energy modeling.
IBM J. Res. Dev.
R. Raghavan, Richard J. Eickemeyer, Aaron Sawdey, John Griswell, D. Parikh, S. Ramani, D. M. Daly, N. Ni, B. Rogers, Alex E. Mericas, L. Maurice, K. Vu
2015 J jnl
IBM POWER8 processor core microarchitecture.
IBM J. Res. Dev.
Balaram Sinharoy, James Van Norstrand, Richard J. Eickemeyer, Hung Q. Le, Jens Leenstra, Dung Q. Nguyen, B. Konigsburg, K. Ward, M. D. Brown, José E. Moreira, D. Levitan, S. Tung, David Hrusecky, James W. Bishop, Michael Gschwind, Maarten Boersma, Michael Kroener, Markus Kaltenbach, Tejas Karkhanis, K. M. Fernsler
2011 A* conf
Abstraction and microarchitecture scaling in early-stage power modeling.
HPCA
Hans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer
2008 J jnl
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches.
IEEE J. Solid State Circuits
Leland Chang, Robert K. Montoye, Yutaka Nakamura, Kevin Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, Damir Jamsek
2005 J jnl
Characterization of simultaneous multithreading (SMT) efficiency in POWER5.
IBM J. Res. Dev.
Harry M. Mathis, Alex E. Mericas, John D. McCalpin, Richard J. Eickemeyer, Steven R. Kunkel
2005 J jnl
POWER5 system microarchitecture.
IBM J. Res. Dev.
Balaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner
2005 A* conf
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.
HPCA
Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
2000 J jnl
A multithreaded PowerPC processor for commercial servers.
IBM J. Res. Dev.
John M. Borkenhagen, Richard J. Eickemeyer, Ronald N. Kalla, Steven R. Kunkel
2000 J jnl
A performance methodology for commercial servers.
IBM J. Res. Dev.
Steven R. Kunkel, Richard J. Eickemeyer, Mikko H. Lipasti, Timothy J. Mullins, Brian O'Krafka, Harold Rosenberg, Steven P. Vanderwiel, Philip L. Vitale, Larry D. Whitley
1997 — conf
Evaluation of Multithreaded Processors and Thread-Switch Policies.
ISHPC
Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Beng-Hong Lim, Mark S. Squillante, Ching-Farn Eric Wu
1996 A* conf
Evaluation of Multithreaded Uniprocessors for Commercial Application Environments.
ISCA
Richard J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante, Shiafun Liu
1994 J jnl
SCISM: A scalable compound instruction set machine.
IBM J. Res. Dev.
Stamatis Vassiliadis, Bart Blaner, Richard J. Eickemeyer
1993 J jnl
A load-instruction unit for pipelined processors.
IBM J. Res. Dev.
Richard J. Eickemeyer, Stamatis Vassiliadis
1992 J jnl
Instruction-level parallelism from execution interlock collapsing.
SIGARCH Comput. Archit. News
Nadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis
1992 A* conf
Interlock collapsing ALU for increased instruction-level parallelism.
MICRO
Nadeem Malik, Richard J. Eickemeyer, Stamatis Vassiliadis
1992 J jnl
On the attributes of the SCISM organization.
SIGARCH Comput. Archit. News
Stamatis Vassiliadis, Bart Blaner, Richard J. Eickemeyer
1988 — —
Performance Evaluation of Multiple Register Set Architectures and Cache Memories
Richard J. Eickemeyer
1988 A* conf
Performance Evaluation of On-Chip Register and Cache Organizations.
ISCA
Richard J. Eickemeyer, Janak H. Patel
1987 A* conf
Performance Evaluation of Multiple Register Sets.
ISCA
Richard J. Eickemeyer, Janak H. Patel