Ricardo Povoa

24 papers A 2B 1C 3Journal 8Unranked 10
YearRankTypeTitle / Venue / Authors
2022 — conf
Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling.
SMACD
Rafael Vieira, Fábio Passos, Ricardo Povoa, Ricardo Martins, Nuno Horta, Jorge Guilherme, Nuno Lourenço
2019 J jnl
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta
2018 — conf
A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications.
SMACD
António Canelas, Ricardo Povoa, Ricardo M. F. Martins, Nuno Lourenço, Jorge Guilherme, Nuno Horta
2018 — conf
An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations.
ICECS
Jigme Zangpo, Ricardo Povoa, Jorge Guilherme, Nuno Horta
2018 A conf
Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel.
DATE
Tiago Pessoa, Nuno Lourenço, Ricardo Martins, Ricardo Povoa, Nuno Horta
2018 J jnl
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology.
Integr.
Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2018 — conf
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs.
SMACD
Fábio Passos, Ricardo Martins, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández
2018 — conf
On the Exploration of Promising Analog IC Designs via Artificial Neural Networks.
SMACD
Nuno Lourenço, Joao Rosa, Ricardo Martins, Helena Aidos, António Canelas, Ricardo Povoa, Nuno Horta
2018 J jnl
Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement.
IEEE Trans. Circuits Syst. II Express Briefs
Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Cavaco Gomes Horta, João Goes
2018 J jnl
Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving.
IEEE Trans. Circuits Syst. II Express Briefs
Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes
2017 A conf
Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing.
DATE
António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
2017 — conf
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks.
SMACD
Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2017 — conf
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization.
SMACD
Nuno C. Lourenço, Ricardo Martins, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2017 — conf
Systematic design of a voltage controlled oscillator using a layout-aware approach.
SMACD
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno C. G. Horta
2016 J jnl
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation.
Integr.
Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Povoa, Nuno Horta
2016 J jnl
Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques.
Integr.
Ricardo Povoa, Ivan Bastos, Nuno Lourenço, Nuno Horta
2016 J jnl
Current-flow and current-density-aware multi-objective optimization of analog IC placement.
Integr.
Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
2016 — conf
Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations.
SMACD
António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
2015 C conf
A voltage-combiners-biased amplifier with enhanced gain and speed using current starving.
ISCAS
Ricardo Povoa, Nuno Lourenço, Nuno Horta, João Goes
2015 J jnl
Floorplan-aware analog IC sizing and optimization based on topological constraints.
Integr.
Nuno Lourenço, António Canelas, Ricardo Povoa, Ricardo Martins, Nuno Horta
2014 — conf
A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner.
ICECS
Ricardo Povoa, Nuno Lourenço, Nuno Horta, Rui Santos-Tavares, João Goes
2014 C conf
LC-VCO automatic synthesis using multi-objective evolutionary techniques.
ISCAS
Ricardo Povoa, Ricardo Lourenco, Nuno Lourenço, António Canelas, Ricardo Martins, Nuno Horta
2013 B conf
A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis.
IEEE Congress on Evolutionary Computation
Frederico Rocha, Nuno Lourenço, Ricardo Povoa, Ricardo Martins, Nuno Horta
2013 C conf
Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners.
VLSI-SoC
Ricardo Povoa, Nuno Lourenço, Nuno Horta, Rui Santos-Tavares, João Goes