Ricardo P. Jasinski

13 papers C 2Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2018 J jnl
A reliable and energy-efficient classifier combination scheme for intrusion detection in embedded systems.
Comput. Secur.
Eduardo Viegas, Altair Olivo Santin, Luiz Oliveira, André França, Ricardo P. Jasinski, Volnei A. Pedroni
2017 J jnl
Towards an Energy-Efficient Anomaly-Based Intrusion Detection Engine for Embedded Systems.
IEEE Trans. Computers
Eduardo Viegas, Altair Olivo Santin, André França, Ricardo P. Jasinski, Volnei A. Pedroni, Luiz S. Oliveira
2016 — conf
Extraction of spatio-temporal features based on a hardware approach for a no-reference objective video quality metric.
BMSB
Marcelo de Oliveira Rosa, Caio Cesar Viana da Silva, Wyllian Bezerra da Silva, Ricardo P. Jasinski, Volnei Antonio Pedroni, Alexandre de Almeida Prado Pohl
2015 C conf
The energy cost of network security: A hardware vs. software comparison.
ISCAS
André Luiz Pereira de França, Ricardo P. Jasinski, Paulo Cemin, Volnei A. Pedroni, Altair Olivo Santin
2012 — conf
A new hardware coprocessor for accelerating Notification-Oriented applications.
FPT
Eduardo Peters, Ricardo P. Jasinski, Volnei A. Pedroni, Jean Marcelo Simão
2011 C conf
A very efficient single-iteration oldest-out data sorter.
ISCAS
Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni
2010 — conf
Achieving near-MLD performance with soft information-set decoders implemented in FPGAs.
APCCAS
Antonio Gortan, Ricardo P. Jasinski, Walter Godoy Jr., Volnei A. Pedroni
2010 — conf
An Improved GF(2) Matrix Inverter with Linear Time Complexity.
ReConFig
Ricardo P. Jasinski, Volnei A. Pedroni, Antonio Gortan, Walter Godoy Jr.
2010 — conf
Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous Counterpart.
ReConFig
Rui A. L. de Cristo, Ricardo P. Jasinski, Volnei A. Pedroni
2010 J jnl
Jari Nurmi: Processor Design - System-on-Chip Computing for ASICs and FPGAs. Springer (2007) ISBN 978-1-4020-5529-4.
Comput. J.
Ricardo P. Jasinski
2010 — conf
Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors.
APCCAS
Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni
2007 J jnl
Fault-Tolerance Techniques for SRAM-Based FPGAs.
Comput. J.
Ricardo P. Jasinski
2004 — conf
Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs.
ISCAS (1)
Fabio Sousa, Volker Mauer, Neimar Duarte, Ricardo P. Jasinski, Volnei A. Pedroni