Ricardo Martins

76 papers A* 2A 6B 2C 7Journal 24Unranked 34

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Comparative Study on the Incorporation of PVT Corner Conditions within Reinforcement Learning-based Analog IC Sizing Approaches. SMACD José Costa, Filipe Azevedo, Ricardo Martins
2025	C	`conf`	An Ultra Low Power Circuits M.Sc. Course Proposal for the GreenChips-EDU Platform. ISCAS Jorge R. Fernandes, Ricardo Martins, Gonçalo Rodrigues, Marcelino B. Santos
2025	—	`conf`	Inverse Analog IC Sizing and Exploration through Diffusion Models and Structural Knowledge. SMACD Filipe Azevedo, Markus Leibl, Ricardo Martins, Helmut Graeb
2025	A*	`conf`	Late Breaking Results: Encoder-Decoder Generative Diffusion Transformer Towards Push-Button Analog IC Sizing. DAC Filipe Azevedo, Nuno Lourenço, Ricardo Martins
2025	—	`conf`	PVT-Inclusive mmWave IC Sizing Optimizations Boosted by ANN-based Performance Regressors and Transfer Learning. ICECS Pedro Paiva, Filipe Azevedo, Ricardo Martins
2025	—	`conf`	Technology-independent Layout Generator of Industry-grade Power Devices Validated Down to 22-nm Nodes. SMACD Duarte Marques, Ricardo Martins, Marcelino B. Santos
2024	—	`conf`	A 25 nW Heartbeat Monitoring Circuit for Wearable Applications in CMOS 65nm. SMACD Rafael Vieira, Seyedehsomayeh Hatefinasab, Ricardo Martins, Nuno Horta, Nuno Lourenço
2024	C	`conf`	An Efficient Performance-Driven Analog IC Placement Optimizer Via Extremely Randomized Tree-Based Post-Layout Performance Regressors. VLSI-SoC Ricardo Martins, Nuno Lourenço
2024	—	`conf`	Effective Routing Probability Maps via Convolutional Neural Networks for Analog IC Layout Automation. SMACD Diogo Peneda, Filipe Azevedo, Nuno Lourenço, Nuno Horta, Ricardo Martins
2024	—	`conf`	Ponderous: A Performance-driven Analog IC Placement Optimizer Leveraged by a ML Pipeline. SMACD Ricardo Martins, António Gusmão, Rafael Vieira, Fábio Passos, Nuno Lourenço, Nuno Horta
2024	—	`conf`	Solving the Inverse Problem of Analog Integrated Circuit Sizing with Diffusion Models. SMACD Pedro Eid, Filipe Azevedo, Ricardo Martins, Nuno Lourenço
2023	—	`conf`	A 23.5-32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology. SMACD Fábio Passos, Nuno Lourenço, Luís Mendes, Ricardo Martins, João Caldinhas Vaz, Nuno Horta
2023	—	`conf`	An ANN-Based Approach to the Modelling and Simulation of Analogue Circuits. SMACD André Amaral, António Gusmão, Rafael Vieira, Ricardo Martins, Nuno Horta, Nuno Lourenço
2023	J	`jnl`	Behavioral Analysis of Noise and Bandwidth Specifications of Heartbeat Detection Circuits for Ultra Low Power Devices. IEEE Access Rafael Vieira, Fábio Passos, Ricardo Martins, Nuno Horta, Nuno Lourenço
2023	—	`conf`	Design Space Exploration of Single-Stage OTAs towards an Ultra-Low-Power LNA for ECG Signals. SMACD Rafael Vieira, Ricardo Martins, Nuno Horta, Nuno Lourenço
2023	—	`conf`	Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models. ASP-DAC Fábio Passos, Nuno Lourenço, Luís Mendes, Ricardo Martins, João Caldinhas Vaz, Nuno Horta
2023	—	`conf`	Paving the Way for the Electronic Design Automation of Power Management Units. SMACD Carlos Santos, Jorge R. Fernandes, Marcelino B. Santos, Ricardo Martins
2022	—	`conf`	ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage. SMACD Pedro Alves, António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins
2022	—	`conf`	Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors. SMACD João Domingues, António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins
2022	—	`conf`	Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling. SMACD Rafael Vieira, Fábio Passos, Ricardo Povoa, Ricardo Martins, Nuno Horta, Jorge Guilherme, Nuno Lourenço
2022	C	`conf`	Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS. ISCAS Luís Mendes, João Caldinhas Vaz, Fábio Passos, Nuno Lourenço, Ricardo Martins
2022	J	`jnl`	DeepPlacer: A custom integrated OpAmp placement tool using deep models. Appl. Soft Comput. António Gusmão, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins
2022	—	`conf`	Machine Learning Approaches for Transformer Modeling. SMACD Fábio Passos, Nuno C. Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2022	—	`conf`	Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/°C Temperature Coefficient. SMACD Nuno Lourenço, Fábio Passos, Rafael Vieira, Ricardo Martins, Nuno Horta, Jorge Guilherme, Ricardo Póvoa
2022	C	`conf`	Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs. ISCAS Pedro Vaz, António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins
2021	J	`jnl`	Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs. IEEE Access António Canelas, Fábio Passos, Nuno Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2021	J	`jnl`	In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization. IEEE Access Luís Mendes, João Caldinhas Vaz, Fábio Passos, Nuno Lourenço, Ricardo Martins
2021	A*	`conf`	Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement. DAC António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins
2021	J	`jnl`	Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test. Integr. Engin Afacan, Nuno Lourenço, Ricardo Martins, Günhan Dündar
2021	J	`jnl`	Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing. Eng. Appl. Artif. Intell. Ricardo Martins, Nuno Lourenço, Ricardo Póvoa, Nuno Horta
2020	J	`jnl`	A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications. IEEE Trans. Circuits Syst. II Express Briefs Ricardo Póvoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes
2020	J	`jnl`	A new family of CMOS inverter-based OTAs for biomedical and healthcare applications. Integr. Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes
2020	—	`book`	Analog IC Placement Generation via Neural Networks from Unlabeled Data António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins
2020	J	`jnl`	Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools. IEEE Trans. Circuits Syst. Ricardo Martins, Nuno Lourenço, Nuno Horta, Shenke Zhong, Jun Yin, Pui-In Mak, Rui Paulo Martins
2020	J	`jnl`	FUZYE: A Fuzzy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. António Canelas, Ricardo Póvoa, Ricardo Martins, Nuno Lourenço, Jorge Guilherme, João Paulo Carvalho, Nuno Horta
2020	J	`jnl`	Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology. IEEE Access Fábio Passos, Elisenda Roca, Ricardo Martins, Nuno Lourenço, Saiyd Ahyoune, Javier J. Sieiro, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2020	C	`conf`	Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender. ISCAS António Gusmão, Fábio Passos, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins
2020	J	`jnl`	Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications. Microelectron. J. Ricardo Póvoa, Richa Arya, António Canelas, Fábio Passos, Ricardo Martins, Nuno Lourenço, Nuno Horta
2019	—	`conf`	A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers. SMACD Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes
2019	—	`conf`	Artificial Neural Networks as an Alternative for Automatic Analog IC Placement. SMACD Daniel Guerra, António Canelas, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins
2019	—	`conf`	Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization. SMACD Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Póvoa, Nuno Horta, Emmanuel Moutaye
2019	J	`jnl`	Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications. IEEE Trans. Very Large Scale Integr. Syst. Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins
2019	—	`conf`	On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects. SMACD Ricardo Martins, Nuno Lourenço, Ricardo Póvoa, Nuno Horta
2019	J	`jnl`	Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta
2019	—	`conf`	Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm. SMACD Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins
2019	—	`conf`	Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing. SMACD Nuno Lourenço, Engin Afacan, Ricardo Martins, Fábio Passos, António Canelas, Ricardo Póvoa, Nuno Horta, Günhan Dündar
2018	—	`conf`	Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications. SMACD Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins
2018	A	`conf`	Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel. DATE Tiago Pessoa, Nuno Lourenço, Ricardo Martins, Ricardo Povoa, Nuno Horta
2018	J	`jnl`	Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. Integr. Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2018	—	`conf`	Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. SMACD Fábio Passos, Ricardo Martins, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández
2018	—	`conf`	On the Exploration of Promising Analog IC Designs via Artificial Neural Networks. SMACD Nuno Lourenço, Joao Rosa, Ricardo Martins, Helena Aidos, António Canelas, Ricardo Povoa, Nuno Horta
2018	J	`jnl`	Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement. IEEE Trans. Circuits Syst. II Express Briefs Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Cavaco Gomes Horta, João Goes
2018	J	`jnl`	Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving. IEEE Trans. Circuits Syst. II Express Briefs Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes
2017	A	`conf`	Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing. DATE António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
2017	—	`conf`	Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks. SMACD Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2017	—	`conf`	New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization. SMACD Nuno C. Lourenço, Ricardo Martins, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2017	J	`jnl`	Stochastic-based placement template generator for analog IC layout-aware synthesis. Integr. Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
2017	—	`conf`	Systematic design of a voltage controlled oscillator using a layout-aware approach. SMACD Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno C. G. Horta
2016	J	`jnl`	AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation. Integr. Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Povoa, Nuno Horta
2016	—	`conf`	Automated analog IC design constraints generation for a layout-aware sizing approach. SMACD Andre Ferreira, Nuno Lourenço, Ricardo Martins, Nuno Horta
2016	J	`jnl`	Current-flow and current-density-aware multi-objective optimization of analog IC placement. Integr. Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
2016	A	`conf`	Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach. DATE David Neves, Ricardo Martins, Nuno Lourenço, Nuno Horta
2016	—	`conf`	On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies. SMACD Ricardo Martins, António Canelas, Nuno Lourenço, Nuno Horta
2016	—	`conf`	Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations. SMACD António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta
2015	C	`conf`	Extraction and application of wiring symmetry rules to route analog multiport terminals. ISCAS Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
2015	J	`jnl`	Floorplan-aware analog IC sizing and optimization based on topological constraints. Integr. Nuno Lourenço, António Canelas, Ricardo Povoa, Ricardo Martins, Nuno Horta
2015	A	`conf`	Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction. DATE Nuno Lourenço, Ricardo Martins, Nuno Horta
2015	J	`jnl`	Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates. Expert Syst. Appl. Ricardo Martins, Nuno Lourenço, Nuno Horta
2014	J	`jnl`	Electromigration-aware analog Router with multilayer multiport terminal structures. Integr. Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
2014	A	`conf`	Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures. DATE Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
2014	C	`conf`	LC-VCO automatic synthesis using multi-objective evolutionary techniques. ISCAS Ricardo Povoa, Ricardo Lourenco, Nuno Lourenço, António Canelas, Ricardo Martins, Nuno Horta
2013	B	`conf`	A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis. IEEE Congress on Evolutionary Computation Frederico Rocha, Nuno Lourenço, Ricardo Povoa, Ricardo Martins, Nuno Horta
2013	—	`conf`	Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel. DoCEIS Frederico Rocha, Ricardo Martins, Nuno Lourenço, Nuno Horta
2013	J	`jnl`	LAYGEN II - Automatic Layout Generation of Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ricardo Martins, Nuno Lourenço, Nuno Horta
2013	B	`conf`	Multi-port multi-terminal analog router based on an evolutionary optimization kernel. IEEE Congress on Evolutionary Computation Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta
2012	A	`conf`	LAYGEN II: automatic analog ICs layout generator based on a template approach. GECCO Ricardo Martins, Nuno Lourenço, Nuno Horta