Reza Sedaghat

35 papers B 1C 2Misc 1Journal 22Unranked 9
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Novel Machine Learning Framework for Covid-19 Image Classification with Bio-heuristic Optimization.
Trans. Comput. Sci.
Prathap Siddavaatam, Reza Sedaghat, Nahid Sahelgozin
2021 J jnl
A New Bio-heuristic Hybrid Optimization for Constrained Continuous Problems.
Trans. Comput. Sci.
Prathap Siddavaatam, Reza Sedaghat
2021 J jnl
Novel Hybrid GWO-WOA and BAT-PSO Algorithms for Solving Design Optimization Problems.
Trans. Comput. Sci.
Noel Jose Thengappurackal Laiju, Reza Sedaghat, Prathap Siddavaatam
2019 J jnl
A New Adaptive Security Architecture with Extensible Computation Complexity for Generic Ciphers.
J. Hardw. Syst. Secur.
Prathap Siddavaatam, Reza Sedaghat
2019 J jnl
Grey Wolf Optimizer Driven design space exploration: A novel framework for multi-objective trade-off in architectural synthesis.
Swarm Evol. Comput.
Prathap Siddavaatam, Reza Sedaghat
2018 J jnl
A Delta-Diagram Based Synthesis for Cross Layer Optimization Modeling of IoT.
Trans. Comput. Sci.
Prathap Siddavaatam, Reza Sedaghat
2017 — conf
intel-LEACH: An optimal framework for node selection using dynamic clustering for wireless sensor networks.
ICITST
Prathap Siddavaatam, Reza Sedaghat, Aakriti Tarun Sharma
2016 B conf
A New Adaptable Construction of Modulo Addition with Scalable Security for Stream Ciphers.
NSS
Min Hsuan Cheng, Reza Sedaghat, Prathap Siddavaatam
2016 — conf
An adaptive security framework with extensible computational complexity for cipher systems.
ICITST
Prathap Siddavaatam, Reza Sedaghat, Min Hsuan Cheng
2015 — conf
Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget.
CCECE
Anirban Sengupta, Reza Sedaghat
2015 J jnl
Optimized Predictive Zonal Search (OPZS) for block-based motion estimation.
Signal Process. Image Commun.
Behnaz Abdoli, Reza Sedaghat, Manuchehr Taghiloo
2015 J jnl
Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budget.
Microelectron. Reliab.
Anirban Sengupta, Reza Sedaghat
2012 J jnl
A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels.
Swarm Evol. Comput.
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
2012 J jnl
Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design.
Microprocess. Microsystems
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
2011 — conf
Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis.
ACAI
Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta
2011 — conf
Integrated design space exploration based on power-performance trade-off using genetic algorithm.
ACAI
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
2011 — conf
Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications.
CCECE
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal
2011 — conf
Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration.
ISQED
Anirban Sengupta, Reza Sedaghat
2011 J jnl
Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP).
Microprocess. Microsystems
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng
2011 — conf
Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis.
CCECE
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal
2011 J jnl
Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems.
Microelectron. Reliab.
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng
2011 J jnl
Switch-level emulation of strength-base soft error detection.
Microelectron. Reliab.
Reza Sedaghat, M. Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe
2010 C conf
A framework for fast design space exploration using fuzzy search for VLSI computing Architectures.
ISCAS
Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta
2010 J jnl
A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective.
Microelectron. Reliab.
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng
2010 C conf
Rapid design space exploration for multi parametric optimization of VLSI designs.
ISCAS
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng
2010 J jnl
Strength violation effect on soft-error detection in sub-micron technology.
Microelectron. Reliab.
M. Reza Javaheri, Reza Sedaghat
2010 J jnl
Switch-level soft error emulation for SET-induced pulses of variable strengths.
Microelectron. J.
Reza Sedaghat, M. Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe
2009 J jnl
Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies.
Microelectron. Reliab.
M. Reza Javaheri, Reza Sedaghat
2008 Misc conf
A Novel Delay Fault Testing Methodology for Resistive Faults in Deep Sub-micron Technologies.
CSICC
M. Reza Javaheri, Reza Sedaghat
2008 J jnl
FPGA-based switch-level fault emulation using module-based dynamic partial reconfiguration.
Microelectron. Reliab.
Peter Ming-Han Lee, Reza Sedaghat
2007 J jnl
Dynamic behavior of resistive faults in nanometer technology.
Microelectron. Reliab.
Mayuri Kunchwar, Reza Sedaghat, Vadim Geurkov
2006 J jnl
FPGA-Based adaptive digital predistortion for radio-over-fiber links.
Microprocess. Microsystems
Hyunsuk Moon, Reza Sedaghat
2006 J jnl
Transistor-level to gate-level comprehensive fault synthesis for n-input primitive gates.
Microelectron. Reliab.
Reza Sedaghat, Mayuri Kunchwar, Raha Abedi, M. Reza Javaheri
2006 J jnl
Verification and fault synthesis algorithm at switch-level.
Microprocess. Microsystems
M. Reza Javaheri, Reza Sedaghat, Leo Kant, Jason Zalev
2003 — conf
A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation.
ISCAS (5)
Reza Sedaghat