Reza Hashemian

36 papers C 3Journal 16Unranked 17
YearRankTypeTitle / Venue / Authors
2024 J jnl
Extended "A Comprehensive and Unified Procedure for Symbolic Analysis of Analog Circuits".
IEEE Trans. Circuits Syst. II Express Briefs
Reza Hashemian
2022 J jnl
A Comprehensive and Unified Procedure for Symbolic Analysis of Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Reza Hashemian
2022 J jnl
Quick Access to Circuit Transfer Functions via NAM Determinant/Cofactors Using UaL Technique.
IEEE Trans. Circuits Syst. II Express Briefs
Reza Hashemian
2021 C conf
Application of Nullors in Symbolic Single Port Transfer Functions Using Admittance Method.
ISCAS
Reza Hashemian
2020 — conf
Constructing Circuit Transfer Functions directly from the State Equations, Using Convolutions.
EIT
Reza Hashemian
2020 J jnl
UaL Decomposition, an Alternative to the LU Factorization of MNA Matrices.
IEEE Trans. Circuits Syst. II Express Briefs
Reza Hashemian
2020 C conf
s-Expanded Transfer Function using UaL Decomposition with Convolution & Deconvolution.
ISCAS
Reza Hashemian
2019 — conf
Design of Analog Circuits for Continuously Changing Constraints Using Fixator Norator Pairs.
MWSCAS
Reza Hashemian
2018 — conf
A Comprehensive Nodal/Branch Circuit Analysis Including Fixator-Norator Pairs in Analog Circuits.
MWSCAS
Reza Hashemian
2018 J jnl
A nullor approach to the design of analog circuits for a desirable performance.
Microelectron. J.
Rohith Krishnan Pilla, S. Krishnakumar, Reza Hashemian
2018 J jnl
Amplifier Design for Specified Frequency Response Profiles Using Nullors-Hearing Aids, a Case Study.
IEEE Trans. Circuits Syst. I Regul. Pap.
Reza Hashemian
2018 J jnl
Fixator-Norator Pair Based Design of Feedback Networks for Analog Amplifier Circuits.
J. Circuits Syst. Comput.
Rohith Krishnan Pilla, S. Krishnakumar, Reza Hashemian
2017 J jnl
Identifying and 3D Displaying Poles and Zeros in Analog Circuit Transfer Functions: Bode Surfaces.
Circuits Syst. Signal Process.
Reza Hashemian, Mounika Vanga, Mahmoud Rahat
2017 — conf
Nullors in amplifier design for bandwidth using multiple feedbacks.
CCECE
Reza Hashemian
2016 — conf
Application of nullors in designing analog circuits for bandwidth.
EIT
Reza Hashemian
2016 J jnl
Finding poles and zeros in an analog circuit directly from its conductance matrix using eigenvalues.
Comput. Electr. Eng.
Reza Hashemian
2016 — conf
RC and RL to LC circuit conversion, and its application in poles and zeros identification.
ICECS
Reza Hashemian
2015 — conf
Identification and extraction of all real axis poles and zeros in RC and RL circuits.
EIT
Reza Hashemian
2015 — conf
S-plane bode plots - identifying poles and zeros in a circuit transfer function.
LASCAS
Reza Hashemian
2014 J jnl
Extraction of Poles and Zeros of an RC Circuit With Roots on the Real Axis.
IEEE Trans. Circuits Syst. II Express Briefs
Reza Hashemian
2014 J jnl
Fixator-Norator Pairs Versus Direct Analytical Tools in Performing Analog Circuit Designs.
IEEE Trans. Circuits Syst. II Express Briefs
Reza Hashemian
2014 — conf
vLab, a high speed multi-accesses parallel processing remote laboratory access for FPGA design technology.
EIT
Kamran Ravanasa, Reza Hashemian
2012 J jnl
Application of Fixator-Norator Pairs in Designing Active Loads and Current Mirrors in Analog Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Reza Hashemian
2010 J jnl
Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs.
VLSI Design
Reza Hashemian
2008 — conf
Use of local biasing in designing analog integrated circuits.
EIT
Reza Hashemian
2007 — conf
FPGA e-Lab, a Technique to Remote Access a Laboratory to Design and Test.
MSE
Reza Hashemian, Jason Riddley
2006 — conf
Designing Analog Circuits with Reduced Biasing Power.
ICECS
Reza Hashemian
2004 — conf
A Hybrid Number System And Its Application In FPGA-DSP Technology.
ITCC (2)
Reza Hashemian, Bipin Sreedharan
2004 J jnl
Condensed table of Huffman coding, a new approach to efficient decoding.
IEEE Trans. Commun.
Reza Hashemian
2003 — conf
Direct Huffman Coding And Decoding Using The Table Of Code-Lengths.
ITCC
Reza Hashemian
1995 J jnl
Memory efficient and high-speed search Huffman coding.
IEEE Trans. Commun.
Reza Hashemian
1994 — conf
Design of a 54-bit adder using a modified Manchester carry chain.
Great Lakes Symposium on VLSI
Reza Hashemian
1993 C conf
High speed search and memory efficient Huffman coding.
ISCAS
Reza Hashemian
1992 — conf
An alternative algorithm for high speed multiplication and addition using growing technique.
Great Lakes Symposium on VLSI
Reza Hashemian
1990 — conf
Parallel Addition Using Pipeline Structure.
ICPP (1)
Reza Hashemian
1990 J jnl
Square Rooting Algorithms for Integer and Floatingg-Point Numbers.
IEEE Trans. Computers
Reza Hashemian