Resve A. Saleh

73 papers A* 6A 5C 9Misc 1Journal 30Unranked 21

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning. IEEE Access Sohaib Majzoub, Resve A. Saleh, Mottaqiallah Taouil, Said Hamdioui, Mohamed Bamakhrama
2022	J	`jnl`	Statistical Properties of the log-cosh Loss Function Used in Machine Learning. CoRR Resve A. Saleh, A. K. Md. Ehsanes Saleh
2021	J	`jnl`	Solution to the Non-Monotonicity and Crossing Problems in Quantile Regression. CoRR Resve A. Saleh, A. K. Md. Ehsanes Saleh
2019	J	`jnl`	Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era. IEEE Access Sohaib Majzoub, Resve A. Saleh, Imran Ashraf, Mottaqiallah Taouil, Said Hamdioui
2011	J	`jnl`	Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations. IEEE Trans. Very Large Scale Integr. Syst. Jeffrey G. Mueller, Resve A. Saleh
2011	—	`conf`	RTL delay macro-modeling with Vt and Vdd variability. IDT Tatsuya Koyagi, Sohaib Majzoub, Masahiro Fukui, Resve A. Saleh
2010	J	`jnl`	Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward
2009	—	`conf`	Active decap design considerations for optimal supply noise reduction. ISQED Xiongfei Meng, Resve A. Saleh
2009	J	`jnl`	An Improved Active Decoupling Capacitor for "Hot-Spot" Supply Noise Reduction in ASIC Designs. IEEE J. Solid State Circuits Xiongfei Meng, Resve A. Saleh
2009	J	`jnl`	Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dipanjan Sengupta, Resve A. Saleh
2009	—	`conf`	Charge-borrowing decap: A novel circuit for removal of local supply noise violations. CICC Xiongfei Meng, Resve A. Saleh, Steven J. E. Wilton
2009	—	`conf`	PVT variation impact on voltage island formation in MPSoC design. ISQED Sohaib Majzoub, Resve A. Saleh, Rabab K. Ward
2009	—	`conf`	Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. SoCC Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward
2009	—	`conf`	Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms. SoC Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Ward
2008	—	`conf`	A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS. ISQED Zahra Sadat Ebadi, Resve A. Saleh
2008	—	`conf`	A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks. ISQED Jeff Mueller, Resve A. Saleh
2008	J	`jnl`	Adaptive Compensation of RF Front-End Nonidealities in Direct Conversion Receivers. IEEE Trans. Circuits Syst. II Express Briefs Zahra Sadat Ebadi, Resve A. Saleh
2008	A*	`conf`	Application-driven floorplan-aware voltage island design. DAC Dipanjan Sengupta, Resve A. Saleh
2008	C	`conf`	Delay macromodeling and estimation for RTL. ISCAS Tatsuya Koyagi, Masahiro Fukui, Resve A. Saleh
2008	J	`jnl`	Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peter Hallschmid, Resve A. Saleh
2008	J	`jnl`	Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Xiongfei Meng, Resve A. Saleh, Karim Arabi
2008	—	`conf`	Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. ISQED Uthman Alsaiari, Resve A. Saleh
2008	Misc	`conf`	Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance. VLSI Design Jeff Mueller, Resve A. Saleh
2008	—	`conf`	Supply voltage selection in Voltage Island based SoC design. SoCC Dipanjan Sengupta, Resve A. Saleh
2007	C	`conf`	A Novel Active Decoupling Capacitor Design in 90nm CMOS. ISCAS Xiongfei Meng, Karim Arabi, Resve A. Saleh
2007	A*	`conf`	Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling. DAC Peter Hallschmid, Resve A. Saleh
2007	—	`conf`	DFM-EDA's Salvation or its Excuse for Being out of Touch with Engineering? ISQED Resve A. Saleh, Pallab K. Chatterjee, Ivan Pesic, Robbert Dobkins, Mike Smayling, Joseph Sawicki
2007	J	`jnl`	Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip. Integr. Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve A. Saleh, André Ivanov
2007	C	`conf`	Essential Fault-Tolerance Metrics for NoC Infrastructures. IOLTS Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve A. Saleh
2007	J	`jnl`	Generalized Power-Delay Metrics in Deep Submicron CMOS Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dipanjan Sengupta, Resve A. Saleh
2007	C	`conf`	Power Reduction of On-Chip Serial Links. ISCAS Amit Kedia, Resve A. Saleh
2007	J	`jnl`	Power Supply Noise in SoCs: Metrics, Management, and Measurement. IEEE Des. Test Comput. Karim Arabi, Resve A. Saleh, Xiongfei Meng
2007	—	`conf`	Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy. ISQED Uthman Alsaiari, Resve A. Saleh
2007	J	`jnl`	Testing Network-on-Chip Communication Fabrics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande
2006	—	`conf`	A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm. ISVLSI Victor O. Aken'Ova, Resve A. Saleh
2006	C	`conf`	A high-speed low-energy dynamic PLA using an input-isolation scheme. ISCAS Reza Molavi, Shahriar Mirabbasi, Resve A. Saleh
2006	—	`conf`	Fast Configuration of an Energy-Efficient Branch Predictor. ISVLSI Peter Hallschmid, Resve A. Saleh
2006	—	`conf`	Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. ISQED Xiongfei Meng, Resve A. Saleh, Karim Arabi
2006	J	`jnl`	System-on-Chip: Reuse and Integration. Proc. IEEE Resve A. Saleh, Steven J. E. Wilton, Shahriar Mirabbasi, Alan J. Hu, Mark R. Greenstreet, Guy Lemieux, Partha Pratim Pande, Cristian Grecu, André Ivanov
2006	C	`conf`	Testable and self-repairable structured logic design. ISCAS Uthman Alsaiari, Resve A. Saleh
2006	J	`jnl`	The application of complex quantized feedback in integrated wireless receivers. IEEE Trans. Circuits Syst. I Regul. Pap. Zahra Sadat Ebadi, Shahriar Mirabbasi, Resve A. Saleh
2005	J	`jnl`	An approach that will NoC your SoCs off! IEEE Des. Test Comput. Resve A. Saleh
2005	—	`conf`	An improved "soft" eFPGA design and implementation strategy. CICC Victor O. Aken'Ova, Guy Lemieux, Resve A. Saleh
2005	J	`jnl`	Design, Synthesis, and Test of Networks on Chips. IEEE Des. Test Comput. Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli
2005	J	`jnl`	Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. IEEE Trans. Computers Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh
2005	—	`conf`	Power-Delay Metrics Revisited for 90nm CMOS Technology. ISQED Dipanjan Sengupta, Resve A. Saleh
2003	—	`conf`	A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers. ISCAS (1) Stephan Shang, Shahriar Mirabbasi, Resve A. Saleh
2003	—	`conf`	Analog IP design flow for SoC applications. ISCAS (4) Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov
2003	—	`conf`	SoC implementation issues for synthesizable embedded programmable logic cores. CICC James C. H. Wu, Victor O. Aken'Ova, Steven J. E. Wilton, Resve A. Saleh
2002	A	`conf`	Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores. ITC Mohsen Nahvi, André Ivanov, Resve A. Saleh
2002	—	`conf`	Trends in Low Power Digital System-on-Chip Designs (invited). ISQED Resve A. Saleh, G. Lim, T. Kadowaki, K. Uchiyama
2000	J	`jnl`	Clock skew verification in the presence of IR-drop in the powerdistribution network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Resve A. Saleh, Syed Zakir Hussain, Steffen Rochel, David Overhauser
1998	A	`conf`	Full-chip verification of UDSM designs. ICCAD Resve A. Saleh, David Overhauser, Sandy Taylor
1996	J	`jnl`	A multifrequency technique for frequency response computation with application to switched-capacitor circuits with nonlinearities. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jeffrey G. Mueller, Brian A. A. Antao, Resve A. Saleh
1996	J	`jnl`	Multilevel and mixed-domain simulation of analog circuits and systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Resve A. Saleh, Brian A. A. Antao, Jaidip Singh
1995	C	`conf`	Improving Parallel Circuit Simulation Using High-Level Waveforms. ISCAS Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh
1994	—	`book`	Mixed-mode simulation and analog multilevel simulation. Resve A. Saleh, Shyh-Jye Jou, A. Richard Newton
1993	J	`jnl`	Improving the performance of parallel relaxation-based circuit simulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gih-Guang Hung, Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh
1992	A*	`conf`	Exact Evaluation of Diagnostic Test Resolution. DAC Ken Kubiak, Steven Parkes, W. Kent Fuchs, Resve A. Saleh
1992	A*	`conf`	Incremental Circuit Simulation Using Waveform Relaxation. DAC Yun-Cheng Ju, Resve A. Saleh
1992	J	`jnl`	Parallel waveform-Newton algorithms for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eugene Z. Xia, Resve A. Saleh
1992	J	`jnl`	Simulation and analysis of transient faults in digital circuits. IEEE J. Solid State Circuits Fred L. Yang, Resve A. Saleh
1991	J	`jnl`	Consistency checking and optimization of macromodels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh
1991	C	`conf`	Identification of Viable Paths Using Binary Decision Diagrams. ICCD Yun-Cheng Ju, Resve A. Saleh
1991	A*	`conf`	Incremental Techniques for the Identification of Statically Sensitizable Critical Paths. DAC Yun-Cheng Ju, Resve A. Saleh
1991	C	`conf`	Parallel Event-Driven Waveform Relaxation. ICCD Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh
1991	A	`conf`	iMACSIM: A Program for Multi-Level Analog Circuit Simulation. ICCAD Jaidip Singh, Resve A. Saleh
1990	J	`jnl`	Accelerating relaxation algorithms for circuit simulation using waveform-Newton and step-size refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Resve A. Saleh, Jacob K. White
1990	A	`conf`	Mixed-Mode Incremental Simulation and Concurrent Fault Simulation. ICCAD Yun-Cheng Ju, Fred L. Yang, Resve A. Saleh
1990	A*	`conf`	Parallel Circuit Simulation Using Hierarchical Relaxation. DAC Gih-Guang Hung, Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh
1990	J	`jnl`	Simulation techniques for mixed analog/digital circuits. IEEE J. Solid State Circuits Eduardo L. Acuna, James P. Dervenis, Andrew J. Pagones, Fred L. Yang, Resve A. Saleh
1989	J	`jnl`	The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Resve A. Saleh, A. Richard Newton
1988	A	`conf`	Compaction of ATPG-generated test sequences for sequential circuits. ICCAD Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh