René Cumplido

104 papers A* 1A 1B 2C 5Journal 54Unranked 34

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Reversible image authentication with efficient block-wise tamper localization. J. Inf. Secur. Appl. Alejandro Peñuelas-Angulo, Claudia Feregrino-Uribe, René Cumplido, Eliú Moreno-Ramírez
2025	J	`jnl`	Adaptive Intrusion Detection System: Hybrid K-Means and Random Forest Approach with Concept Drift Detection. Computación y Sistemas (CyS) Eric Garcia-Huitzitl, Lázaro Bustio-Martínez, René Cumplido
2024	J	`jnl`	A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms. Microprocess. Microsystems Martín Letras, Alicia Morales-Reyes, René Cumplido, María-Guadalupe Martínez-Peñaloza, Claudia Feregrino-Uribe
2024	J	`jnl`	Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+. ACM Trans. Reconfigurable Technol. Syst. Jonathan Lopez-Valdivieso, René Cumplido
2023	J	`jnl`	A secure DWT-based dual watermarking scheme for image authentication and copyright protection. Multim. Tools Appl. A. Hernández-Joaquín, G. Melendez-Melendez, René Cumplido
2023	J	`jnl`	An adaptive method for prevention of overflow in reversible data hiding schemes. Expert Syst. Appl. Alejandro Peñuelas-Angulo, Claudia Feregrino-Uribe, René Cumplido
2023	J	`jnl`	An adaptive pixel value ordering based reversible data hiding scheme for images. Expert Syst. Appl. G. Melendez-Melendez, Alicia Morales-Reyes, René Cumplido
2022	J	`jnl`	A lightweight data representation for phishing URLs detection in IoT environments. Inf. Sci. Lázaro Bustio-Martínez, Miguel Ángel Álvarez-Carmona, Vitali Herrera-Semenets, Claudia Feregrino-Uribe, René Cumplido
2022	J	`jnl`	FPGA/GPU-based Acceleration for Frequent Itemsets Mining: A Comprehensive Review. ACM Comput. Surv. Lázaro Bustio-Martínez, René Cumplido, Martín Letras, Raudel Hernández-León, Claudia Feregrino-Uribe, José Hernández-Palancar
2022	—	`conf`	Reversible Image Authentication Scheme with Tampering Reconstruction Based on Very Deep Super Resolution Network. MICAI (1) G. Melendez-Melendez, René Cumplido
2021	J	`jnl`	A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks. J. Sensors Miguel Morales-Sandoval, Luis Armando Rodriguez Flores, René Cumplido, Jose Juan Garcia-Hernandez, Claudia Feregrino, Ignacio Algredo-Badillo
2021	J	`jnl`	IP-cores watermarking scheme at behavioral level using genetic algorithms. Eng. Appl. Artif. Intell. Jorge Echavarria, Alicia Morales-Reyes, René Cumplido, Miguel A. Salido, Claudia Feregrino-Uribe
2020	J	`jnl`	On the design of hardware architectures for parallel frequent itemsets mining. Expert Syst. Appl. Martín Letras, Lázaro Bustio-Martínez, René Cumplido, Raudel Hernández-León, Claudia Feregrino-Uribe
2019	—	`ed.`	2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019 ReConFig David Andrews, René Cumplido, Claudia Feregrino, Marco Platzner
2019	J	`jnl`	A novel multi-core algorithm for frequent itemsets mining in data streams. Pattern Recognit. Lett. Lázaro Bustio-Martínez, Alfredo Muñoz-Briseño, René Cumplido, Raudel Hernández-León, Claudia Feregrino-Uribe
2019	—	`conf`	Detection And Localization Of Splicing Attacks On Videos Using Block Correlation. PACRIM Ernesto Aparicio-Díaz, René Cumplido, Lázaro Bustio-Martínez, Claudia Feregrino-Uribe
2019	J	`jnl`	Guest Editorial: Special Issue on Reconfigurable Computing and FPGA Technology. J. Parallel Distributed Comput. René Cumplido, Maya B. Gokhale, Claudia Feregrino, Michael Hübner
2019	J	`jnl`	Temporal Copy-Move Forgery Detection and Localization Using Block Correlation Matrix. J. Intell. Fuzzy Syst. Ernesto Aparicio-Díaz, René Cumplido, Maikel L. Pérez Gort, Claudia Feregrino-Uribe
2019	J	`jnl`	Using hashing and lexicographic order for Frequent Itemsets Mining on data streams. J. Parallel Distributed Comput. Lázaro Bustio-Martínez, Mauro Martín Letras Luna, René Cumplido, Raudel Hernández-León, Claudia Feregrino-Uribe, José Manuel Bande Serrano
2018	—	`ed.`	2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018 ReConFig David Andrews, René Cumplido, Claudia Feregrino, Dirk Stroobandt
2018	J	`jnl`	An FPGA-based programmable processor for bilinear pairings. IACR Cryptol. ePrint Arch. Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido
2018	J	`jnl`	On the design of hardware-software architectures for frequent itemsets mining on data streams. J. Intell. Inf. Syst. Lázaro Bustio-Martínez, René Cumplido, Raudel Hernández-León, José Manuel Bande Serrano, Claudia Feregrino-Uribe
2017	—	`conf`	A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption. LASCAS Luis Armando Rodriguez Flores, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino-Uribe, Ignacio Algredo-Badillo
2017	—	`conf`	Approximate frequent itemsets mining on data streams using hashing and lexicographie order in hardware. LASCAS Lázaro Bustio-Martínez, René Cumplido, Mauro Martín Letras Luna, Claudia Feregrino-Uribe, Raudel Hernández-León, José Manuel Bande Serrano
2017	J	`jnl`	Improving the construction of ORB through FPGA-based acceleration. Mach. Vis. Appl. Roberto de Lima, José Martínez-Carranza, Alicia Morales-Reyes, René Cumplido
2016	J	`jnl`	A scalable and customizable processor array for implementing cellular genetic algorithms. Neurocomputing Martín Letras, Alicia Morales-Reyes, René Cumplido
2016	—	`conf`	An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter. IPDPS Workshops Juan Andrés Pérez-Celis, José Martínez-Carranza, Alicia Morales-Reyes, Claudia Feregrino-Uribe, René Cumplido
2016	—	`conf`	Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning. IPDPS Workshops Martín Letras, Raudel Hernández-León, René Cumplido
2016	—	`ed.`	International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, November 30 - Dec. 2, 2016 ReConFig Peter M. Athanas, René Cumplido, Claudia Feregrino, Ron Sass
2016	J	`jnl`	Introduction to the Special Section on FPGAs Technology and Applications. Comput. Electr. Eng. René Cumplido, Peter Athanas, Eduardo de la Torre
2016	J	`jnl`	Introduction to the special section on FPGAs Technology and Applications. Comput. Electr. Eng. René Cumplido, Michael Hübner, Michael J. Wirthlin
2015	J	`jnl`	A fast hardware software platform for computing irreducible testors. Expert Syst. Appl. Vladimir Rodríguez-Diez, José Francisco Martínez Trinidad, Jesús Ariel Carrasco-Ochoa, Manuel Lazo-Cortés, Claudia Feregrino-Uribe, René Cumplido
2015	—	`conf`	Accelerating the construction of BRIEF descriptors using an FPGA-based architecture. ReConFig Roberto de Lima, José Martínez-Carranza, Alicia Morales-Reyes, René Cumplido
2015	A	`conf`	An Empirical Analysis on Dimensionality in Cellular Genetic Algorithms. GECCO Alicia Morales-Reyes, Hugo Jair Escalante, Martín Letras, René Cumplido
2015	J	`jnl`	An analysis of computational models for accelerating the subtractive pixel adjacency model computation. Comput. Electr. Eng. Marisol Rodriguez-Perez, Alicia Morales-Reyes, René Cumplido, Claudia Feregrino-Uribe
2015	—	`conf`	Frequent Itemsets Mining in Data Streams Using Reconfigurable Hardware. NFMCP Lázaro Bustio, René Cumplido, Raudel Hernández-León, José Manuel Bande Serrano, Claudia Feregrino
2015	—	`ed.`	International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Riviera Maya, Mexico, December 7-9, 2015 ReConFig Michael Hübner, Maya B. Gokhale, René Cumplido
2015	J	`jnl`	Introduction to Special issue on Reconfigurable computing and FPGAs. Microprocess. Microsystems René Cumplido, Eduardo de la Torre, Claudia Feregrino-Uribe, Michael J. Wirthlin
2015	—	`conf`	Message from chairs. ReConFig Maya B. Gokhale, Michael Hübner, René Cumplido
2015	J	`jnl`	Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs. Microprocess. Microsystems Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido
2014	J	`jnl`	A compact FPGA-based processor for the Secure Hash Algorithm SHA-256. Comput. Electr. Eng. Rommel García, Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido
2014	—	`conf`	A hardware architecture for filtering irreducible testors. ReConFig Vladimir Rodriguez, José F. Martínez, Jesús Ariel Carrasco-Ochoa, Manuel Sabino Lazo-Cortés, René Cumplido, Claudia Feregrino-Uribe
2014	—	`conf`	FSM merging and reduction for IP cores watermarking using Genetic Algorithms. ReConFig Jorge Echavarria, Alicia Morales-Reyes, René Cumplido, Miguel A. Salido
2014	J	`jnl`	Hardware architecture for security improved Fallahpour audio watermarking scheme. IEICE Electron. Express Claudia Feregrino-Uribe, Ernesto Aparicio-Díaz, José Juan García-Hernández, Alejandra Menendez-Ortiz, René Cumplido, Alicia Morales-Reyes
2014	J	`jnl`	Introduction to Special issue on FPGA Devices and Applications. Microprocess. Microsystems Peter M. Athanas, René Cumplido, Claudia Feregrino-Uribe, Eduardo de la Torre
2014	J	`jnl`	Introduction to the special issue on FPGA Technology and Applications. Comput. Electr. Eng. Peter Athanas, René Cumplido, Eduardo de la Torre
2014	J	`jnl`	Synthesizing VHDL from Activity Models in UML 2. Int. J. Circuit Theory Appl. Tomás Balderas-Contreras, René Cumplido, Gustavo Rodríguez Gómez
2014	C	`conf`	The Evaluation of Ordered Features for SMS Spam Filtering. CIARP José Manuel Bande Serrano, José Hernández-Palancar, René Cumplido
2013	—	`conf`	A parallelization methodology for reconfigurable systems applied to edge detection. ReCoSoC Juan M. Campos, René Cumplido, Claudia Feregrino-Uribe, Roberto Perez-Andrade
2013	—	`conf`	A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m. ReCoSoC Eduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino-Uribe, Ignacio Algredo-Badillo
2013	J	`jnl`	Area/performance trade-off analysis of an FPGA digit-serial Comput. Electr. Eng. Miguel Morales-Sandoval, Claudia Feregrino-Uribe, Paraskevas Kitsos, René Cumplido
2013	J	`jnl`	FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. Microprocess. Microsystems Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval
2013	—	`conf`	High Throughput Signature Based Platform for Network Intrusion Detection. CIARP (2) José Manuel Bande Serrano, José Hernández-Palancar, René Cumplido
2013	J	`jnl`	High payload data-hiding in audio signals based on a modified OFDM approach. Expert Syst. Appl. Jose Juan Garcia-Hernandez, Ramón Parra-Michel, Claudia Feregrino-Uribe, René Cumplido
2013	J	`jnl`	Introduction to the special section on 19th reconfigurable architectures workshop (RAW 2012). ACM Trans. Reconfigurable Technol. Syst. Diana Goehringer, René Cumplido
2013	J	`jnl`	Multi-character cost-effective and high throughput architecture for content scanning. Microprocess. Microsystems José Manuel Bande Serrano, José Hernández-Palancar, René Cumplido
2013	J	`jnl`	On an external memory scheme for processor arrays. IEICE Electron. Express Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos
2013	—	`conf`	Processor arrays generation for matrix algorithms used in embedded platforms. ReConFig Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos
2013	—	`conf`	RAW Introduction. IPDPS Workshops Jürgen Becker, Ramachandran Vaidyanathan, Peter Athanas, Marco D. Santambrogio, René Cumplido, Oliver Sander
2013	J	`jnl`	Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011). Int. J. Reconfigurable Comput. René Cumplido, Peter Athanas, Jürgen Becker
2013	C	`conf`	Video Error Concealment Based on Data Hiding for the Emerging Video Technologies. PSIVT Francisco Aguirre-Ramos, Claudia Feregrino-Uribe, René Cumplido
2012	J	`jnl`	A multi-cycle fixed point square root module for FPGAs. IEICE Electron. Express Fernando Martin del Campo, Alicia Morales-Reyes, Roberto Perez-Andrade, René Cumplido, Aldo G. Orozco-Lugo, Claudia Feregrino
2012	J	`jnl`	Hardware-software platform for computing irreducible testors. Expert Syst. Appl. Alejandro Rojas, René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino, José Francisco Martínez Trinidad
2012	—	`conf`	RAW Introduction. IPDPS Workshops Jürgen Becker, Jinian Bian, Christophe Bobda, René Cumplido, Michael Hübner
2012	—	`conf`	Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm. ISVLSI Ignacio Algredo-Badillo, Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido
2012	J	`jnl`	Watermarking using similarities based on fractal codification. Digit. Signal Process. Pedro Aaron Hernandez-Avalos, Claudia Feregrino-Uribe, René Cumplido
2011	—	`ed.`	2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011 ReConFig Peter M. Athanas, Jürgen Becker, René Cumplido
2011	—	`conf`	Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware - Experiences on teaching and research. ReCoSoC René Cumplido, Claudia Feregrino-Uribe, Jose Juan Garcia-Hernandez
2011	C	`conf`	Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms. DSD Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval
2011	—	`conf`	On a Hybrid and General Control Scheme for Algorithms Represented as a Polytope. IPDPS Workshops Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos
2011	J	`jnl`	On the Implementation of a Hardware Architecture for an Audio Data Hiding System. J. Signal Process. Syst. Jose Juan Garcia-Hernandez, Claudia Feregrino-Uribe, René Cumplido, Carolina Reta
2011	—	`conf`	RAW Introduction. IPDPS Workshops Jürgen Becker, Pascal Benoit, René Cumplido
2010	—	`conf`	A Highly Parallel Algorithm for Frequent Itemset Mining. MCPR Alejandro Mesa, Claudia Feregrino-Uribe, René Cumplido, José Hernández-Palancar
2010	J	`jnl`	A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation. J. Circuits Syst. Comput. Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido, Ignacio Algredo-Badillo
2010	B	`conf`	A UML 2.0 Profile to Model Block Cipher Algorithms. ECMFA Tomás Balderas-Contreras, Gustavo Rodríguez Gómez, René Cumplido
2010	J	`jnl`	A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter. Digit. Signal Process. Roberto Perez-Andrade, René Cumplido, Claudia Feregrino-Uribe, Fernando Martin del Campo
2010	J	`jnl`	Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard. Comput. Electr. Eng. Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval
2010	J	`jnl`	Hardware architecture for adaptive filtering based on energy-CFAR processor for radar target detection. IEICE Electron. Express Santos López-Estrada, René Cumplido
2010	J	`jnl`	Improving the security of Fallahpour's audio watermarking scheme. IEICE Electron. Express Jose Juan Garcia-Hernandez, Claudia Feregrino-Uribe, René Cumplido, Ramón Parra-Michel
2010	—	`conf`	On the Design of a Hardware-Software Architecture for Acceleration of SVM's Training Phase. MCPR Lázaro Bustio-Martínez, René Cumplido, José Hernández-Palancar, Claudia Feregrino-Uribe
2010	—	`ed.`	ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings ReConFig Viktor K. Prasanna, Jürgen Becker, René Cumplido
2010	—	`conf`	Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems. Dynamically Reconfigurable Architectures René Cumplido, Juan M. Campos, Claudia Feregrino-Uribe, Jose Roberto Perez-Andrade
2009	—	`conf`	A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication. ENC Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido, Ignacio Algredo-Badillo
2009	J	`jnl`	A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation. Int. J. Reconfigurable Comput. Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo
2009	J	`jnl`	A versatile linear insertion sorter based on an FIFO scheme. Microelectron. J. Roberto Perez-Andrade, René Cumplido, Claudia Feregrino-Uribe, Fernando Martin del Campo
2009	J	`jnl`	An area/performance trade-off analysis of a GF(2 Comput. Electr. Eng. Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido, Ignacio Algredo-Badillo
2009	J	`jnl`	Efficient implementation of the RDM-QIM algorithm in an FPGA. IEICE Electron. Express Jose Juan Garcia-Hernandez, Carolina Reta, René Cumplido, Claudia Feregrino-Uribe
2009	—	`conf`	FPGA-architecture for Knowledge-Based Target Detection in Radar Signal Processing. ERSA Santos López-Estrada, René Cumplido
2009	—	`ed.`	ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings ReConFig Viktor K. Prasanna, Lionel Torres, René Cumplido
2008	—	`conf`	A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation. ReConFig Zobeida Jezabel Guzman-Zavaleta, Claudia Feregrino-Uribe, René Cumplido
2008	—	`conf`	A Versatile Linear Insertion Sorter Based on a FIFO Scheme. ISVLSI Roberto Perez-Andrade, René Cumplido, Fernando Martin del Campo, Claudia Feregrino-Uribe
2008	B	`conf`	A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. FPL Roberto Perez-Andrade, René Cumplido, Claudia Feregrino-Uribe, Fernando Martin del Campo
2008	J	`jnl`	Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description. IEICE Trans. Inf. Syst. Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval
2008	—	`conf`	FPGA Hardware Architecture of the Steganographic ConText Technique. CONIELECOMP Edgar Gomez-Hernández, Claudia Feregrino-Uribe, René Cumplido
2008	—	`conf`	FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. ReConFig Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval
2008	—	`conf`	FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems. ReConFig Jose Juan Garcia-Hernandez, Claudia Feregrino-Uribe, René Cumplido
2008	—	`conf`	Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers. ReConFig Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo
2008	J	`jnl`	On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm. Comput. Electr. Eng. Tomás Balderas-Contreras, René Cumplido, Claudia Feregrino-Uribe
2007	C	`conf`	FPGA-Based Architecture for Computing Testors. IDEAL Alejandro Rojas, René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino-Uribe, José Francisco Martínez Trinidad
2006	—	`conf`	Decision Tree Based FPGA-Architecture for Texture Sea State Classification. ReConFig Santos López-Estrada, René Cumplido
2006	—	`conf`	Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture. ICCSA (3) Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido
2006	C	`conf`	On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification. CIARP René Cumplido, Jesús Ariel Carrasco-Ochoa, Claudia Feregrino
2005	J	`jnl`	A high-performance processor for embedded real-time control. IEEE Trans. Control. Syst. Technol. René Cumplido, Simon R. Jones, Roger Goodall, Stephen Bateman
2005	A*	`conf`	High performance encryption cores for 3G networks. DAC Tomás Balderas-Contreras, René Cumplido