Renshen Wang

26 papers A* 1A 2B 1C 1Journal 8Unranked 12
YearRankTypeTitle / Venue / Authors
2023 — conf
FormNetV2: Multimodal Graph Contrastive Learning for Form Document Information Extraction.
ACL (1)
Chen-Yu Lee, Chun-Liang Li, Hao Zhang, Timothy Dozat, Vincent Perot, Guolong Su, Xiang Zhang, Kihyuk Sohn, Nikolay Glushnev, Renshen Wang, Joshua Ainslie, Shangbang Long, Siyang Qin, Yasuhisa Fujii, Nan Hua, Tomas Pfister
2023 J jnl
FormNetV2: Multimodal Graph Contrastive Learning for Form Document Information Extraction.
CoRR
Chen-Yu Lee, Chun-Liang Li, Hao Zhang, Timothy Dozat, Vincent Perot, Guolong Su, Xiang Zhang, Kihyuk Sohn, Nikolai Glushnev, Renshen Wang, Joshua Ainslie, Shangbang Long, Siyang Qin, Yasuhisa Fujii, Nan Hua, Tomas Pfister
2023 — conf
Text Reading Order in Uncontrolled Conditions by Sparse Graph Segmentation.
ICDAR (6)
Renshen Wang, Yasuhisa Fujii, Alessandro Bissacco
2023 J jnl
Text Reading Order in Uncontrolled Conditions by Sparse Graph Segmentation.
CoRR
Renshen Wang, Yasuhisa Fujii, Alessandro Bissacco
2022 — conf
FormNet: Structural Encoding beyond Sequential Modeling in Form Document Information Extraction.
ACL (1)
Chen-Yu Lee, Chun-Liang Li, Timothy Dozat, Vincent Perot, Guolong Su, Nan Hua, Joshua Ainslie, Renshen Wang, Yasuhisa Fujii, Tomas Pfister
2022 J jnl
FormNet: Structural Encoding beyond Sequential Modeling in Form Document Information Extraction.
CoRR
Chen-Yu Lee, Chun-Liang Li, Timothy Dozat, Vincent Perot, Guolong Su, Nan Hua, Joshua Ainslie, Renshen Wang, Yasuhisa Fujii, Tomas Pfister
2022 A conf
Post-OCR Paragraph Recognition by Graph Convolutional Networks.
WACV
Renshen Wang, Yasuhisa Fujii, Ashok C. Popat
2022 B conf
Unified Line and Paragraph Detection by Graph Convolutional Networks.
DAS
Shuang Liu, Renshen Wang, Michalis Raptis, Yasuhisa Fujii
2022 J jnl
Unified Line and Paragraph Detection by Graph Convolutional Networks.
CoRR
Shuang Liu, Renshen Wang, Michalis Raptis, Yasuhisa Fujii
2021 J jnl
General-Purpose OCR Paragraph Identification by Graph Convolution Networks.
CoRR
Renshen Wang, Yasuhisa Fujii, Ashok C. Popat
2021 — conf
ROPE: Reading Order Equivariant Positional Encoding for Graph-based Document Information Extraction.
ACL/IJCNLP (2)
Chen-Yu Lee, Chun-Liang Li, Chu Wang, Renshen Wang, Yasuhisa Fujii, Siyang Qin, Ashok C. Popat, Tomas Pfister
2021 J jnl
ROPE: Reading Order Equivariant Positional Encoding for Graph-based Document Information Extraction.
CoRR
Chen-Yu Lee, Chun-Liang Li, Chu Wang, Renshen Wang, Yasuhisa Fujii, Siyang Qin, Ashok C. Popat, Tomas Pfister
2012 — conf
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip.
ISPD
Renshen Wang, Nimish Shah
2011 J jnl
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham
2010 J jnl
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness.
ACM Trans. Design Autom. Electr. Syst.
Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng
2010 — —
Physical planning to embrace interconnect dominance in power and performance.
Renshen Wang
2010 — conf
Physical synthesis of bus matrix for high bandwidth low power on-chip communications.
ISPD
Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng
2009 A* conf
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
DAC
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng
2009 — conf
Noise minimization during power-up stage for a multi-domain power network.
ASP-DAC
Wanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan Arani, Renshen Wang, Zhi Zhu, Chung-Kuan Cheng
2009 — conf
Octilinear redistributive routing in bump arrays.
ACM Great Lakes Symposium on VLSI
Renshen Wang, Chung-Kuan Cheng
2009 — conf
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design.
ACM Great Lakes Symposium on VLSI
Renshen Wang, Chung-Kuan Cheng
2009 C conf
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations.
ICCD
Renshen Wang, Takumi Okamoto, Chung-Kuan Cheng
2008 — conf
3-D floorplanning using labeled tree and dual sequences.
ISPD
Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng
2008 — conf
Low Power Passive Equalizer Design for Computer Memory Links.
Hot Interconnects
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng
2006 A conf
Layer minimization of escape routing in area array packaging.
ICCAD
Renshen Wang, Rui Shi, Chung-Kuan Cheng
2005 — conf
An improved P-admissible floorplan representation based on Corner Block List.
ASP-DAC
Renshen Wang, Sheqin Dong, Xianlong Hong