Renato Stefanelli

41 papers A 1C 6Misc 2Journal 18Unranked 12

Year	Rank	Type	Title / Venue / Authors
2011	J	`jnl`	A New Compact SD2 Positive Integer Triangular Array Division Circuit. IEEE Trans. Very Large Scale Integr. Syst. Marco D. Santambrogio, Renato Stefanelli
2002	—	`conf`	Fault-Tolerant CAM Architectures: A Design Framework. DFT Fabio Salice, Mariagiovanna Sami, Renato Stefanelli
1998	—	`conf`	Systematic AUED Codes for Self-Checking Architectures. DFT Donatella Sciuto, Cristina Silvano, Renato Stefanelli
1997	—	`conf`	Array partitioning to achieve defect tolerance. EUROMICRO Fausto Distante, Mariagiovanna Sami, Renato Stefanelli
1997	—	`conf`	Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. DFT Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli
1997	—	`conf`	Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance. DFT Fausto Distante, Mariagiovanna Sami, Renato Stefanelli
1996	—	`conf`	Fault detection and fault tolerance issues at CMOS level through AUED encoding. DFT Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
1996	—	`conf`	KITE: a behavioural approach to fault-tolerance in FPGA-based systems. DFT Giovanni A. Mojoli, Davide Salvi, M. G. Sami, Giacomo R. Sechi, Renato Stefanelli
1995	—	`conf`	A Channel-Constrained Reconfiguration Approach for Processing Arrays. DFT Mariagiovanna Sami, Fausto Distante, Renato Stefanelli
1995	Misc	`conf`	A new switching-level approach to multiple-output functions synthesis. VLSI Design Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
1994	—	`conf`	A CMOS Fault Tolerant Architecture for Swith-Level Faults. DFT Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
1994	C	`conf`	CMOS Reliability Improvements Through a New Fault Tolerant Technique. ISCAS Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
1994	J	`jnl`	Innovative Structures for CMOS Combinational Gates Synthesis. IEEE Trans. Computers Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
1993	J	`jnl`	Concurrently self-checking structures for Fsms. Microprocess. Microprogramming M. G. Sami, Donatella Sciuto, Renato Stefanelli
1993	C	`conf`	Multi-parallel convolvers. IEEE Symposium on Computer Arithmetic Luigi Dadda, Vincenzo Piuri, Renato Stefanelli
1993	Misc	`conf`	New CMOS Structures for the Synthesis of Dominant Functions. VLSI Design Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
1993	—	`conf`	System Level Policies for Fault Tolerance Issues in the FERMI Project. DFT A. Dell'Acqua, M. Hansen, Sami J. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, Aurore Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, Simona Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson
1993	—	`ed.`	The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 27-29, 1993, Venice, Italy, Proceedings DFT Fabrizio Lombardi, Mariagiovanna Sami, Yvon Savaria, Renato Stefanelli
1992	J	`jnl`	A behavioral approach to testability analysis for neural networks. Microprocess. Microprogramming Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto, Renato Stefanelli
1992	J	`jnl`	Fault-tolerant techniques for VLSI tree structures. Microprocess. Microprogramming Vincenzo Piuri, Renato Stefanelli
1991	J	`jnl`	Concurrent error detection in parallel multipliers and complex arithmetic structures: Remarks on the use of the 3n code. Microprocessing and Microprogramming Vincenzo Piuri, Renato Stefanelli
1991	J	`jnl`	Mapping neural nets onto a massively parallel architecture: a defect-tolerance solution. Proc. IEEE Fausto Distante, Mariagiovanna Sami, Renato Stefanelli, Giancarlo Storti-Gajan
1991	—	`conf`	Optimization techniques for multiple output function synthesis. EURO-DAC Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
1991	J	`jnl`	The PAPIA system. J. VLSI Signal Process. Virginio Cantoni, V. Gesu, Marco Ferretti, Stefano Levialdi, Roberto M. Negrini, Renato Stefanelli
1990	J	`jnl`	Area compaction in silicon structures for neural net implementation. Microprocessing and Microprogramming Fausto Distante, M. G. Sami, Renato Stefanelli, Giancarlo Storti Gajani
1989	—	`book`	Fault-tolerance through reconfiguration of VLSI and WSI awards. Roberto M. Negrini, Mariagiovanna Sami, Renato Stefanelli
1989	J	`jnl`	Reconfiguration of VLSI arrays by covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fabrizio Lombardi, Mariagiovanna Sami, Renato Stefanelli
1988	J	`jnl`	An algorithm for functional reconfiguration of fixed-size arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli
1988	J	`jnl`	Error detection in serial multipliers and in systolic arrays: An approach based upon A★N codes. Microprocess. Microprogramming Vincenzo Piuri, Renato Stefanelli, Giovanni Traverso
1988	C	`conf`	Use of redundant binary representation for fault-tolerant arithmetic array processors. ICCD Vincenzo Piuri, Renato Stefanelli
1987	C	`ed.`	8th IEEE Symposium on Computer Arithmetic, ARITH 1987, Como, Italy, May 18-21, 1987 IEEE Symposium on Computer Arithmetic Mary Jane Irwin, Renato Stefanelli
1987	A	`conf`	A Technique for Reconfiguring Two Dimensional VLSI Arrays. RTSS Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli
1986	J	`jnl`	A comment on an investigation into the skeletonization approach of Hilditch. Pattern Recognit. Renato Stefanelli
1986	J	`jnl`	Fault Tolerance Fechniques for Array Structures Used in Supercomputing. Computer Roberto M. Negrini, Mariagiovanna Sami, Renato Stefanelli
1986	J	`jnl`	Reconfigurable architectures for VLSI processing arrays. Proc. IEEE Mariagiovanna Sami, Renato Stefanelli
1985	C	`conf`	PAPIA: Pyramidal architecture for parallel image analysis. IEEE Symposium on Computer Arithmetic Virginio Cantoni, Marco Ferretti, Stefano Levialdi, Renato Stefanelli
1983	C	`conf`	A multiplier with multiple error correction capability. IEEE Symposium on Computer Arithmetic Marco Annaratone, Renato Stefanelli
1983	—	`conf`	Reconfigurable architectures for VLSI processing arrays. AFIPS National Computer Conference Mariagiovanna Sami, Renato Stefanelli
1973	J	`jnl`	Compression algorithms that preserve basic topological features in binary-coded patterns. Pattern Recognit. Mariagiovanna Sami, Renato Stefanelli
1972	J	`jnl`	A Suggestion for a High-Speed Parallel Binary Divider. IEEE Trans. Computers Renato Stefanelli
1971	J	`jnl`	Some Parallel Thinning Algorithms for Digital Pictures. J. ACM Renato Stefanelli, Azriel Rosenfeld