Renate Merker - RankMe

45 papers A 3B 2C 3Misc 1Journal 6Unranked 28

Year	Rank	Type	Title / Venue / Authors
2011	J	`jnl`	A Cost Model for Partial Dynamic Reconfiguration. Trans. High Perform. Embed. Archit. Compil. Markus Rullmann, Renate Merker
2010	—	`ch.`	Design Methods and Tools for Improved Partial Dynamic Reconfiguration. Dynamically Reconfigurable Systems Markus Rullmann, Renate Merker
2009	B	`conf`	An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. FPL Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2008	—	`conf`	A cost model for partial dynamic reconfiguration. ICSAMOS Markus Rullmann, Renate Merker
2008	B	`conf`	Fine grain reconfigurable architectures. FPL Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
2008	—	`conf`	Synthesis of efficiently reconfigurable datapaths for reconfigurable computing. FPT Markus Rullmann, Renate Merker
2008	C	`conf`	Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. DSD Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich
2007	A	`conf`	A Reconfiguration Aware Circuit Mapper for FPGAs. IPDPS Markus Rullmann, Renate Merker
2007	—	`conf`	Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
2006	—	`conf`	An Architecture Description Language for Massively Parallel Processor Architectures. MBMV Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker
2006	—	`conf`	Derivation of Packing Instructions for Exploiting Sub-Word Parallelism. PARELEC Rainer Schaffer, Renate Merker, Francky Catthoor
2006	—	`conf`	Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead. ARCS Workshops Markus Rullmann, Renate Merker
2006	—	`conf`	Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints. Euro-Par Sebastian Siegel, Renate Merker
2006	—	`conf`	Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels. PARELEC Sebastian Siegel, Rainer Schaffer, Renate Merker
2006	A	`conf`	Maximum edge matching for reconfigurable computing. IPDPS Markus Rullmann, Renate Merker
2006	—	`conf`	Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy. ASAP Sebastian Siegel, Renate Merker
2006	—	`conf`	Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism. ICSAMOS Rainer Schaffer, Renate Merker
2005	—	`conf`	Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys
2005	A	`conf`	Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching. IPDPS Markus Rullmann, Sebastian Siegel, Renate Merker
2004	—	`conf`	A Parallel Hardware-Software System for Signal Processing Algorithms. PARELEC Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, Renate Merker, Jürgen Kelber
2004	—	`conf`	Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays. PARELEC Sebastian Siegel, Renate Merker
2004	—	`conf`	Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling. Interaction between Compilers and Computer Architectures Jan Müller, Dirk Fimmel, Renate Merker
2004	—	`conf`	Optimal Loop Scheduling with Register Constraints Using Flow Graphs. ISPAN Jan Müller, Dirk Fimmel, Renate Merker
2004	—	`conf`	Optimized Data-Reuse in Processor Arrays. ASAP Sebastian Siegel, Renate Merker
2003	J	`jnl`	A Hardware-Software System for Tomographic Reconstruction. J. Circuits Syst. Comput. Jan Müller, Dirk Fimmel, Renate Merker, Rainer Schaffer
2003	C	`conf`	Causality Constraints for Processor Architectures with Sub-Word Parallelism. DSD Rainer Schaffer, Renate Merker, Francky Catthoor
2002	—	`conf`	Systematic Design of Programs with Sub-Word Parallelism. PARELEC Rainer Schaffer, Renate Merker, Francky Catthoor
2001	J	`jnl`	Design of Processor Arrays for Reconfigurable Architectures. J. Supercomput. Dirk Fimmel, Renate Merker
2000	—	`conf`	Application of Partitioning Methods for the Design of Parallel Programs for a System of Digital Signal Processors. PARELEC Mathias Kortke, Thomas Schmitt, Renate Merker
2000	Misc	`conf`	Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. VLSI Design Rainer Schaffer, Renate Merker, Francky Catthoor
2000	J	`jnl`	Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. Parallel Algorithms Appl. Rainer Schaffer, Francky Catthoor, Renate Merker
2000	—	`conf`	High-Level Synthesis System (HLDESA) for Processor Arrays. PARELEC Renate Merker
1999	J	`jnl`	Hierarchical algorithm partitioning at system level for an improved utilization of memory structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Uwe Eckhardt, Renate Merker
1999	—	`conf`	Localization of Data Transfer in Processor Arrays. Euro-Par Dirk Fimmel, Renate Merker
1999	—	`conf`	Parallel Processor Array for Tomographic Reconstruction Algorithms. EUROCAST Thomas Schmitt, Dirk Fimmel, Mathias Kortke, Renate Merker
1999	—	`conf`	Parallelization of Algorithms for a System of Digital Signal Processors. EUROMICRO Mathias Kortke, Dirk Fimmel, Renate Merker
1998	—	`conf`	Design of Processor Arrays for Real-Time Applications. Euro-Par Dirk Fimmel, Renate Merker
1998	J	`jnl`	Determination of processor allocation in the design of processor arrays. Microprocess. Microsystems Dirk Fimmel, Renate Merker
1997	—	`conf`	A System for Designing Parallel Processor Arrays. EUROCAST Renate Merker, Ulrich Eckhardt, Dirk Fimmel, H. Schreiber
1997	—	`conf`	Determination of the Processor Functionality in the Design of Processor Arrays. ASAP Dirk Fimmel, Renate Merker
1997	—	`conf`	Optimization of the Background Memory Utilization by Partitioning. ISSS Uwe Eckhardt, Renate Merker
1997	—	`conf`	Scheduling in Co-Partitioned Array Architectures. ASAP Uwe Eckhardt, Renate Merker
1996	C	`conf`	Propagation of I/O-Variables in Massively Parallel Processor Arrays. PDP Dirk Fimmel, Renate Merker
1994	—	`conf`	Systematic Generation of a Variety of Processor Arrays. Parcella A. Schubert, Renate Merker, H. Schreiber
1990	—	`—`	Systematischer Entwurf und Modellbildung systolischer Arrays. Renate Merker