Ren-Song Tsay - RankMe

71 papers A* 5A 11B 2C 1Misc 4Journal 21Unranked 27

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	A Secure Decentralized Key Backup and Social Recovery Method. ICCE-Taiwan Nian-Zu Wang, Ren-Song Tsay
2024	—	`conf`	Accelerate Large Language Model Inference on Edge TPU with OpenVX framework. AICAS You-En Wu, Hsin-I Wu, Kuo-Cheng Chin, Yi-Chun Yang, Ren-Song Tsay
2024	B	`conf`	Beyond Time-Quantum: A Basic-Block FDA Approach for Accurate System Computing Performance Estimation. ASPDAC Hsuan-Yi Lin, Ren-Song Tsay
2023	—	`conf`	A Decentralized Solution for Secure Management of IoT Access Rights. ICR Yi-Chun Yang, Ren-Song Tsay
2023	—	`conf`	A Secure and Reliable Private Key Recovery Method. ICCE-Taiwan Wei-Hsin Chang, Ren-Song Tsay
2023	—	`conf`	Ureka: A Decentralized and Secure System for Managing Personal IoT Devices. ICCE-Taiwan Yi-Chun Yang, Ren-Song Tsay
2022	—	`conf`	An Adaptive High-Performance Quantization Approach for Resource-Constrained CNN Inference. AICAS Hsu-Hsun Chin, Ren-Song Tsay, Hsin-I Wu
2022	—	`conf`	An Embedded CNN Design for Edge Devices Based on Logarithmic Computing. VLSI-DAT Chong-Yin Lu, Ren-Song Tsay, Weyshin Chang
2022	J	`jnl`	An Owner-managed Indirect-Permission Social Authentication Method for Private Key Recovery. CoRR Wei-Hsin Chang, Ren-Song Tsay
2021	J	`jnl`	3LSAA: A Secure And Privacy-preserving Zero-knowledge-based Data-sharing Approach Under An Untrusted Environment. CoRR Wei-Yi Kuo, Ren-Song Tsay
2021	J	`jnl`	A Double-Linked Blockchain Approach Based on Proof-of-Refundable-Tax Consensus Algorithm. CoRR Zheng-Xun Jiang, Ren-Song Tsay
2021	J	`jnl`	A Fast-and-Effective Early-Stage Multi-level Cache Optimization Method Based on Reuse-Distance Analysis. CoRR Cheng-Lin Tsai, Ren-Song Tsay
2021	J	`jnl`	A High-Performance Adaptive Quantization Approach for Edge CNN Applications. CoRR Hsu-Hsun Chin, Ren-Song Tsay, Hsin-I Wu
2021	J	`jnl`	A Precise Program Phase Identification Method Based on Frequency Domain Analysis. CoRR Hsuan-Yi Lin, Ren-Song Tsay
2021	J	`jnl`	An Effective Early Multi-core System Shared Cache Design Method Based on Reuse-distance Analysis. CoRR Hsin-Yu Ho, Ren-Song Tsay
2021	J	`jnl`	An Effective Parallel Program Debugging Approach Based on Timing Annotation. CoRR Yun Chang, Hsin-I Wu, Ren-Song Tsay
2021	J	`jnl`	Analytical Process Scheduling Optimization for Heterogeneous Multi-core Systems. CoRR Chien-Hao Chen, Ren-Song Tsay
2021	J	`jnl`	Automatic Timing-Coherent Transactor Generation for Mixed-level Simulations. CoRR Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay
2020	—	`conf`	A Heuristic Region-based Concurrency Bug Testing Approach. ISPA/BDCloud/SocialCom/SustainCom Kuo-Cheng Chin, Ren-Song Tsay, Hsin-I Wu
2020	—	`conf`	A Pipeline-Based Scheduler for Optimizing Latency of Convolution Neural Network Inference over Heterogeneous Multicore Systems. AICAS Hsin-I Wu, Da-Yi Guo, Hsu-Hsun Chin, Ren-Song Tsay
2020	J	`jnl`	A Very Compact Embedded CNN Processor Design Based on Logarithmic Computing. CoRR Tsung-Ying Lu, Hsu-Hsun Chin, Hsin-I Wu, Ren-Song Tsay
2020	J	`jnl`	A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Intercomponent Interactions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsin-I Wu, Da-Yi Guo, Ren-Song Tsay
2020	—	`conf`	An Optimal Slack-Based Course Scheduling Algorithm for Personalised Study Plans. ICEIT Asheen Lateilla Richards, Ren-Song Tsay
2020	—	`conf`	CORONA: A k-COnnected RObust Interconnection Network Generation Algorithm. VLSI-DAT Hsin-I Wu, Ren-Song Tsay, Fong-Yuan Chang
2020	—	`conf`	Designing A Compact Convolutional Neural Network Processor on Embedded FPGAs. GCAIoT Yin-Chun Ling, Hsu-Hsun Chin, Hsin-I Wu, Ren-Song Tsay
2020	Misc	`conf`	VIRA: a virtualization assisted deterministic system-level simulations. SAC Hsin-I Wu, Ren-Song Tsay, Hsu-Hsun Chin
2018	A	`conf`	A highly efficient full-system virtual prototype based on virtualization-assisted approach. DATE Hsin-I Wu, Chi-Kang Chen, Tsung-Ying Lu, Ren-Song Tsay
2016	—	`conf`	An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. ICHI Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay
2016	Misc	`conf`	An accurate and flexible early memory system power evaluation approach using a microcomponent method. CODES+ISSS Chi-Kang Chen, Hsin-I Wu, Chi-Ting Hsiao, Ren-Song Tsay
2016	—	`conf`	Poster Paper: An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. ICHI Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay
2015	—	`conf`	AROMA: A highly accurate microcomponent-based approach for embedded processor power analysis. ASP-DAC Zih-Ci Huang, Chi-Kang Chen, Ren-Song Tsay
2015	—	`conf`	Automatic timing-coherent transactor generation for mixed-level simulations. ASP-DAC Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay
2015	J	`jnl`	Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jyun-Hao Chang, Hsin-I Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak
2014	A	`conf`	An activity-sensitive contention delay model for highly efficient deterministic full-system simulations. DATE Shu-Yung Chen, Chien-Hao Chen, Ren-Song Tsay
2013	—	`conf`	A Cycle Count Accurate TLM bus modeling approach. VLSI-DAT Mao Lin Li, Chen Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay
2013	C	`conf`	A basic-block power annotation approach for fast and accurate embedded software power estimation. VLSI-SoC Chien-Min Lee, Chi-Kang Chen, Ren-Song Tsay
2013	A	`conf`	A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations. DATE Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee, Ren-Song Tsay
2013	J	`jnl`	A distributed timing synchronization technique for parallel multi-core instruction-set simulation. ACM Trans. Embed. Comput. Syst. Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay
2013	—	`conf`	A fast and accurate instruction-oriented processor simulation approach. VLSI-DAT Pei-Chia Patty Lin, Evason Du, Ren-Song Tsay
2013	—	`conf`	A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules. ASP-DAC Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen
2013	—	`conf`	An efficient hybrid synchronization technique for scalable multi-core instruction set simulations. ASP-DAC Bo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang
2013	J	`jnl`	Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus. ACM Trans. Embed. Comput. Syst. Chen Kang Lo, Mao Lin Li, Li-Chun Chen, Yi-Shan Lu, Ren-Song Tsay, Hsu-Yao Huang, Jen-Chieh Yeh
2013	J	`jnl`	MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen
2012	A*	`conf`	A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation. DAC Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, Ren-Song Tsay
2012	J	`jnl`	An Extended SystemC Framework for Efficient HW/SW Co-Simulation. ACM Trans. Design Autom. Electr. Syst. Meng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay
2011	A*	`conf`	A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation. DAC Meng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay
2011	A	`conf`	A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems. DATE Cheng-Yang Fu, Meng-Huan Wu, Ren-Song Tsay
2011	—	`conf`	Cut-demand based routing resource allocation and consolidation for routability enhancement. ASP-DAC Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak
2011	A	`conf`	Cycle-count-accurate processor modeling for fast and accurate system-level simulation. DATE Chen Kang Lo, Li-Chun Chen, Meng-Huan Wu, Ren-Song Tsay
2011	A	`conf`	DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive scheduling. DATE Peng-Chih Wang, Meng-Huan Wu, Ren-Song Tsay
2011	—	`conf`	From academic ideas to practical physical design tools. ISPD Ren-Song Tsay
2011	J	`jnl`	Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform. J. Signal Process. Syst. Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay, Cyuan-Jhe Wu
2010	A	`conf`	Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation. DATE Meng-Huan Wu, Wen-Chuan Lee, Chen-Yu Chuang, Ren-Song Tsay
2010	—	`conf`	Source-level timing annotation for fast and accurate TLM computation model generation. ASP-DAC Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay
2009	Misc	`conf`	An effective synchronization approach for fast and accurate multi-core instruction-set simulation. EMSOFT Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay
2009	—	`conf`	Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model. ASP-DAC Chen Kang Lo, Ren-Song Tsay
2009	Misc	`conf`	Cycle count accurate memory modeling in system level design. CODES+ISSS Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
2009	A	`conf`	How to consider shorts and guarantee yield rate improvement for redundant wire insertion. ICCAD Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak
2008	—	`conf`	A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology. SiPS Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay
2008	B	`conf`	Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video. ICIP Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Rong Chen, Rong Yang, Ren-Song Tsay
2007	—	`conf`	An Entrepreneurship Emulation Platform. MSE Ren-Song Tsay
1993	J	`jnl`	An exact zero-skew clock routing algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ren-Song Tsay
1992	—	`conf`	Clock tree regeneration. Great Lakes Symposium on VLSI Jan-Ming Ho, Ren-Song Tsay
1992	A*	`conf`	Performance-Driven System Partitioning on Multi-Chip Modules. DAC Minshine Shih, Ernest S. Kuh, Ren-Song Tsay
1991	J	`jnl`	A new method for floor planning using topological constraint reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gopalakrishnan Vijayan, Ren-Song Tsay
1991	A*	`conf`	An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement. DAC Ren-Song Tsay, Jürgen Koehl
1991	A	`conf`	Exact Zero Skew. ICCAD Ren-Song Tsay
1990	A	`conf`	Floorplanning by Topological Constraint Reduction. ICCAD Gopalakrishnan Vijayan, Ren-Song Tsay
1989	A	`conf`	A new approach to sea-of-gates global routing. ICCAD Tai-Ming Parng, Ren-Song Tsay
1988	J	`jnl`	PROUD: a sea-of-gates placement algorithm. IEEE Des. Test Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu
1988	A*	`conf`	Proud: A Fast Sea-of-Gates Placement Algorithm. DAC Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu