Remy Cellier

16 papers C 2Misc 1Journal 3Unranked 10
YearRankTypeTitle / Venue / Authors
2025 — conf
A Programmable, Negative, and Dynamically Biased Sampler for Ultra-Low Power Body-Bias Generators in 18nm FD-SOI.
DCIS
Tom Bergmann, Joel Damiens, Alfonso Hildebrand Rueda, Stephane Lacouture, Remy Cellier, Nacer Abouchi
2024 — conf
Advanced Analog Design Optimization: Comparison Between Reinforcement Learning and Heuristic Algorithms.
SMACD
Michel Chevalier, Severin Trochut, Roberto Guizzetti, Pascal Urard, Lioua Labrak, John Samuel, Remy Cellier, Nacer Abouchi
2024 Misc conf
Artificial neural network-based solution for PSP MOSFET model card extraction.
VLSID
Alba Ordonez Rodriguez, Fabien Gilibert, Francois Paolini, Pascal Urard, Roberto Guizzetti, John Samuel, Remy Cellier, Lioua Labrak, Bastien Deveautour
2023 — conf
Reinforcement Learning for Analog Sizing Optimization.
SMACD
Michel Chevalier, Severin Trochut, Roberto Guizzetti, Pascal Urard, Lioua Labrak, John Samuel, Remy Cellier, Nacer Abouchi
2019 — conf
Body-biasing considerations with SPAD FDSOI: advantages and drawbacks.
ESSDERC
Tulio Chaves de Albuquerque, Dylan Issartel, Raphael Clerc, Patrick Pittet, Remy Cellier, Wilfried Uhring, Andreia Cathelin, Françis Calmon
2018 — conf
An integrated 10MHz 3 States Buck converter for fast transient response in 180nm CMOS.
DCIS
Arnaud Toni, Hassan Ihs, Taner Dosluoglu, Remy Cellier, Nacer Abouchi
2016 C conf
A single switch resonant and quasi-resonant converter suitable for low power applications.
IECON
Nicolas Quentin, Remi Perrin, Christian Martin, Charles Joubert, Louis Grimaud, Bertrand Lacombe, Remy Cellier
2015 J jnl
A 0.35 um CMOS Operational Amplifier Using Multi-Path Frequency Compensation.
J. Low Power Electron.
Remy Cellier, Pawel Fiedorow
2015 J jnl
A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time ΣΔ ADC for a Digital Closed-Loop Class-D Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Achille Donida, Remy Cellier, Angelo Nagari, Piero Malcovati, Andrea Baschirotto
2015 — conf
A time-integration based quenching circuit for Geiger-mode avalanche diodes.
NEWCAS
M. M. Vignetti, Françis Calmon, Remy Cellier, Patrick Pittet, Laurent Quiquerez, Aurore Savoy-Navarro
2015 J jnl
Design guidelines for the integration of Geiger-mode avalanche diodes in standard CMOS technologies.
Microelectron. J.
M. M. Vignetti, Françis Calmon, Remy Cellier, Patrick Pittet, Laurent Quiquerez, Aurore Savoy-Navarro
2013 — conf
A 40-nm CMOS, 1.1-V, 101-dB DR, 1.7-mW continuous-time ΣΔ ADC for a digital closed-loop class-D amplifier.
ICECS
Achille Donida, Piero Malcovati, Remy Cellier, Angelo Nagari, Andrea Baschirotto
2012 — conf
A synchronized self oscillating Class-D amplifier for mobile application.
ESSCIRC
Remy Cellier, Angelo Nagari, Souha Hacine, Gaël Pillonnet, Nacer Abouchi
2011 — conf
Analysis and design of an analog control loop for digital input class D amplifiers.
ICECS
Remy Cellier, Gaël Pillonnet, Nacer Abouchi, Roberto M'Rad, Angelo Nagari
2009 C conf
A 0.01%THD, 70dB PSRR Single Ended Class D using Variable Hysteresis Control for Headphone Amplifiers.
ISCAS
Gaël Pillonnet, Nacer Abouchi, Remy Cellier, Angelo Nagari
2008 — conf
A topological comparison of PWM and hysteresis controls in switching audio amplifiers.
APCCAS
Gaël Pillonnet, Remy Cellier, Emmanuel Allier, Nacer Abouchi, Angelo Nagari