Rekha K. James

29 papers A 3C 5Misc 1Journal 9Unranked 11

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Exploiting virtual channel allocation policies in STT-RAM buffers of NoC routers through hardware Trojan. J. Syst. Archit. Josna Philomina, Rekha K. James, Palash Das, Shirshendu Das, Daleesha M. Viswanathan
2026	J	`jnl`	NeSTAR: Hardware Trojans and its mitigation strategy in NoC routers. Integr. Josna Philomina, Rekha K. James, Shirshendu Das, Palash Das, Daleesha M. Viswanathan
2025	J	`jnl`	RAESC: A Reconfigurable AES Countermeasure Architecture for RISC-V With Enhanced Power Side-Channel Resilience. IEEE Comput. Archit. Lett. Nayana Rajeev, Cathrene Biju, Titu Mary Ignatius, Roy Paily Palathinkal, Rekha K. James
2024	J	`jnl`	Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-Chip. J. Circuits Syst. Comput. Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose
2023	J	`jnl`	ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training. IEEE Des. Test K. Neethu, K. C. Sharin Shahana, Rekha K. James, John Jose, Sumit K. Mandal
2023	J	`jnl`	Modelling and Impact Analysis of Antipode Attack in Bufferless On-Chip Networks. SN Comput. Sci. Rose George Kunthara, V. R. Josna, K. Neethu, Rekha K. James, John Jose
2023	—	`conf`	Modelling and Impact Analysis of Push Back Attack in 3D Bufferless Network on Chip. MCSoC V. R. Josna, Rose George Kunthara, Rekha K. James, John Jose
2022	—	`conf`	DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks. ACM Great Lakes Symposium on VLSI Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose
2022	C	`conf`	RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC. VLSI-SoC Akshay Sarman, Alwin Shaju, Rose George Kunthara, K. Neethu, Rekha K. James, John Jose
2022	Misc	`conf`	Threshold Voltage Modeling of Negative Capacitance Double Gate TFET. VLSID U. S. Shikha, Rekha K. James, Anju Pradeep, Sumi Baby, Jobymol Jacob
2021	—	`conf`	Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links. VDAT S. Sharon Dev, S. M. Krishna, S. S. Archana, Rose George Kunthara, K. Neethu, Rekha K. James
2021	J	`jnl`	Traffic aware routing in 3D NoC using interleaved asymmetric edge routers. Nano Commun. Networks Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose
2019	—	`conf`	2L-2D Routing for Buffered Mesh Network-on-Chip. VDAT Rose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, Tripti S. Warrier, John Jose
2019	—	`conf`	Asymmetric routing in 3D NoC using interleaved edge routers. NoCArc@MICRO Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose
2019	C	`conf`	DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip. TENCON Rose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, John Jose
2018	—	`conf`	ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs. ISED Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose
2018	J	`jnl`	Token based Detection and Neural Network based Reconstruction framework against code injection vulnerabilities. J. Inf. Secur. Appl. Teresa K. George, K. Poulose Jacob, Rekha K. James
2018	C	`conf`	Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. VLSI-SoC Simi Zerine Sleeba, John Jose, Maurizio Palesi, Rekha K. James, Maniyelil Govindankutty Mini
2016	J	`jnl`	A GA Based Simple and Efficient Technique to Design Combinational Logic Circuits Using Universal Logic Modules. J. Circuits Syst. Comput. C. K. Vijayakumari, Rekha K. James, P. Mythili
2016	—	`conf`	Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths. ACM Great Lakes Symposium on VLSI Tuhin Subhra Chakraborty, Santanu Kundu, Deepak Agrawal, Sanjay Tanaji Shinde, Jacob Mathews, Rekha K. James
2009	A	`conf`	Double Digit Decimal Multiplier on XILINX FPGA. ESA Rekha K. James, K. Poulose Jacob, Sreela Sasi
2009	—	`conf`	High Performance, Low Latency Double Digit Decimal Multiplier on ASIC and FPGA. NaBIC Rekha K. James, K. Poulose Jacob, Sreela Sasi
2008	C	`conf`	Dual-mode RNS based programmable decimation filter for WCDMA and WLANa. ISCAS Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi
2008	C	`conf`	Fixed Point Decimal Multiplication Using RPS Algorithm. ISPA Rekha K. James, Shahana Thottathikkulam Kassim, K. Poulose Jacob, Sreela Sasi
2008	—	`conf`	RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX. VTC Spring Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi
2008	—	`conf`	RRNS-Convolutional encoded concatenated code for OFDM based wireless communication. ICON Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi
2007	—	`conf`	A New Look at Reversible Logic Implementation of Decimal Adder. SoC Rekha K. James, Shahana Thottathikkulam Kassim, K. Poulose Jacob, Sreela Sasi
2007	A	`conf`	Genetic Algorithm-Based Combinational Logic Synthesis Using Universal Logic Modules. ESA Shahana Thottathikkulam Kassim, Rekha K. James, K. Poulose Jacob, Sreela Sasi
2006	A	`conf`	Delay-Reduced Combinational Logic Synthesis using Multiplexers. ESA Rekha K. James, Shahana Thottathikkulam Kassim, K. Poulose Jacob, Sreela Sasi