Reiner W. Hartenstein

115 papers A* 3A 6B 20C 5Misc 4Journal 25Unranked 48

Year	Rank	Type	Title / Venue / Authors
2013	—	`conf`	The tunnel vision syndrome: Massively delaying progress. ASAP Reiner W. Hartenstein
2008	—	`conf`	The von Neumann Syndrome and the CS Education Dilemma. ARC Reiner W. Hartenstein
2007	—	`conf`	The Neumann Syndrome calls for a revolution. HPRCTA Reiner W. Hartenstein
2006	A	`conf`	Flexibility and low power: a contradiction in terms? ISLPED Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson
2006	B	`conf`	From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. FPL Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein
2006	—	`conf`	From Organic Computing to Reconfigurable Supercomputing. ARCS Workshops Reiner W. Hartenstein
2006	J	`jnl`	Mehr Effizienz durch Configware: auch für Supercomputing. Prax. Inf.verarb. Kommun. Reiner W. Hartenstein
2006	—	`ch.`	Morphware and Configware. Handbook of Nature-Inspired and Innovative Computing Reiner W. Hartenstein
2006	J	`jnl`	Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic. ACM Trans. Design Autom. Electr. Syst. Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein
2006	A	`conf`	RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances. IPDPS Reiner W. Hartenstein
2006	—	`conf`	The re-definition of low power design for HPC: a paradigm shift. SBCCI Reiner W. Hartenstein
2006	—	`conf`	Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. ReCoSoC Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein
2005	B	`conf`	FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. FPL Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein
2004	—	`conf`	Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic. SBCCI Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis Gustavo A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein
2004	—	`conf`	Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming. WOB Ricardo P. Jacobi, Mauricio Ayala-Rincón, Luis Gustavo A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein
2004	Misc	`conf`	The changing role of computer architecture education within CS curricula: invited presentation. WCAE Reiner W. Hartenstein
2004	—	`conf`	The digital divide of computing. Conf. Computing Frontiers Reiner W. Hartenstein
2003	A	`conf`	Are We Really Ready for the Breakthrough? IPDPS Reiner W. Hartenstein
2003	J	`jnl`	Configware and morphware going mainstream. J. Syst. Archit. Jürgen Becker, Reiner W. Hartenstein
2003	—	`conf`	Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments. SCCC Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein
2003	—	`conf`	Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic. SBCCI Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein
2003	C	`conf`	Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing. FDL Mauricio Ayala-Rincón, Ricardo P. Jacobi, Carlos H. Llanos, Reiner W. Hartenstein
2002	—	`conf`	Applying ELAN Strategies in Simulating Processors over Simple Architectures. WRS Mauricio Ayala-Rincón, Rinaldi Maya Neto, Ricardo P. Jacobi, Carlos H. Llanos, Reiner W. Hartenstein
2002	J	`jnl`	Architectural Specification, Exploration and Simulation Through Rewriting-Logic. Rev. Colomb. de Computación Mauricio Ayala-Rincón, Reiner W. Hartenstein, Rinaldi Maya Neto, Ricardo P. Jacobi, Carlos H. Llanos
2002	B	`conf`	Disruptive Trends by Data-Stream-Based Computing. FPL Reiner W. Hartenstein
2002	—	`conf`	Memory addressing organization for stream-based reconfigurable computing. ICECS Michael Herz, Reiner W. Hartenstein, Miguel Miranda, Erik Brockmeyer, Francky Catthoor
2002	—	`conf`	Trends in reconfigurable logic and reconfigurable computing. ICECS Reiner W. Hartenstein
2001	A	`conf`	A decade of reconfigurable computing: a visionary retrospective. DATE Reiner W. Hartenstein
2001	—	`conf`	Coarse grain reconfigurable architecture (embedded tutorial). ASP-DAC Reiner W. Hartenstein
2001	C	`conf`	Reconfigurable Computing: A New Business Model and its Impact on SoC Design. DSD Reiner W. Hartenstein
2000	—	`conf`	Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. PATMOS Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger
2000	B	`ed.`	Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings FPL Reiner W. Hartenstein, Herbert Grünbacher
2000	B	`conf`	Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. FPL Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
2000	—	`conf`	KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. ASP-DAC Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
2000	A	`conf`	Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). FPGA Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
1999	B	`conf`	An Internet Based Development Framework for Reconfigurable Computing. FPL Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann
1999	—	`conf`	Configware: From Glue Logic Synthesis to Reconfigurable Computing Systems- Introduction. HICSS Reiner W. Hartenstein, Veljko M. Milutinovic
1999	B	`ed.`	Field-Programmable Logic and Applications, 9th International Workshop, FPL'99, Glasgow, UK, August 30 - September 1, 1999, Proceedings FPL Patrick Lysaght, James Irvine, Reiner W. Hartenstein
1999	B	`conf`	Mapping Applications onto Reconfigurable Kress Arrays. FPL Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
1998	B	`conf`	Designing for Xilinx XC6200 FPGAs. FPL Reiner W. Hartenstein, Michael Herz, Frank Gilbert
1998	B	`conf`	Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators. FPL Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
1998	B	`ed.`	Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings FPL Reiner W. Hartenstein, Andres Keevallik
1998	—	`conf`	Introduction to the Configware Minitrack: Hardware and Software Come Closer. HICSS (7) Reiner W. Hartenstein
1998	—	`conf`	On Reconfigurable Co-processing Units. IPPS/SPDP Workshops Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
1998	—	`conf`	Parallelization in Co-Compilation for Configurable Accelerators. ASP-DAC Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger
1998	C	`conf`	Real-Time Prototyping in Microprocessor/Accelerator Symbiosis. International Workshop on Rapid System Prototyping Jürgen Becker, Reiner W. Hartenstein
1997	—	`conf`	A Novel Sequencer Hardware for Application Specific Computing. ASAP Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
1997	—	`conf`	A Novel Universal Sequencer Hardware. ARCS Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
1997	—	`conf`	A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. HICSS (5) Reiner W. Hartenstein, Jürgen Becker
1997	B	`conf`	An operating system for custom computing machines based on the Xputer paradigm. FPL Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger
1997	B	`conf`	Data scheduling to increase performance of parallel accelerators. FPL Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
1997	Misc	`conf`	Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. VLSI Design Reiner W. Hartenstein, Jürgen Becker
1997	—	`conf`	Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. CODES Reiner W. Hartenstein, Jürgen Becker
1997	J	`jnl`	Seeking Solutions in Configurable Computing. Computer William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
1996	—	`conf`	A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
1996	—	`conf`	A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
1996	—	`conf`	An Embedded Accelerator for Real-Time Image Processing. RTS Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1996	Misc	`conf`	CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
1996	B	`conf`	Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. FPL Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1996	B	`ed.`	Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 6th International Workshop on Field-Programmable Logic, FPL '96, Darmstadt, Germany, September 23-25, 1996, Proceedings FPL Reiner W. Hartenstein, Manfred Glesner
1996	J	`jnl`	High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
1996	—	`book`	Null Bock auf High Tech - Arbeitsplatz-Export: nur weil die Löhne zu hoch sind? Reiner W. Hartenstein
1996	—	`conf`	Two-Level Hardware/Software Partitioning Using CoDe-X. ECBS Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1996	—	`conf`	Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. CODES Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1995	—	`conf`	A Parallelizing Compilation Method for the Map-oriented Machine. ASAP Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt
1995	—	`conf`	A datapath synthesis system for the reconfigurable datapath architecture. ASP-DAC Reiner W. Hartenstein, Rainer Kress
1995	Misc	`conf`	Combining structural and procedural programming by parallelizing compilation. SAC Reiner W. Hartenstein, Karin Schmidt
1995	J	`jnl`	Custom Computing Machines - Das aktuelle Schlagwort Inform. Spektrum Reiner W. Hartenstein
1995	J	`jnl`	Hardware/Software Co-Design - Das aktuelle Schlagwort Inform. Spektrum Reiner W. Hartenstein
1994	B	`conf`	A New FPGA Architecture for Word-Oriented Datapaths. FPL Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
1994	—	`conf`	A dynamically reconfigurable wavefront array architecture for evaluation of expressions. ASAP Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
1994	B	`conf`	Data-Procedural Languages for FPL-based Machines. FPL Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
1994	B	`ed.`	Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings FPL Reiner W. Hartenstein, Michal Servít
1994	—	`book`	Wozu noch Mikro-Chips? - Einführung in Methoden der Technischen Informatik zur Anwendung der Mikroelektronik für die Wettbewerbsfähigkeit unserer Wirtschaft: Sachbuch und Textbuch. Reiner W. Hartenstein
1993	J	`jnl`	CMOS interconnect modelling for timing analysis. Microprocess. Microprogramming Rainer Kress, Elmar U. K. Melcher, Reiner W. Hartenstein, Michel Dana
1993	B	`ed.`	Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31 - September 2, 1992, Selected Papers FPL Herbert Grünbacher, Reiner W. Hartenstein
1992	J	`jnl`	A novel paradigm of parallel computation and its use to implement simple high-performance hardware. Future Gener. Comput. Syst. Reiner W. Hartenstein, Alexander G. Hirschbiel, Karin Schmidt, Michael Weber
1992	—	`conf`	An Information Model Describing the Exchange of IC Technology Data. Electronic Design Automation Frameworks Joachim Blödel, Markus Brandstetter, Peter Conradi, Walter Drangmeister, Reiner W. Hartenstein, Dietmar Schroeder
1992	B	`conf`	Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. FPL Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
1991	J	`jnl`	A novel ASIC design approach based on a new machine paradigm. IEEE J. Solid State Circuits Reiner W. Hartenstein, Alexander G. Hirschbiel, Michael Riedmüller, Karin Schmidt, Michael Weber
1991	J	`jnl`	Gemeinsame Stellungnahme der Fakultätentage Elektrotechnik und Informatik zur Abstimmung ihrer Fachgebierte im Bereich Informationstechnik. Inform. Spektrum Franz-Josef Brandenburg, Werner Freise, Winfried Görke, Reiner W. Hartenstein, P. Kühn, H. J. Schmitt
1990	—	`conf`	A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware. CONPAR Reiner W. Hartenstein, Alexander G. Hirschbiel, Michael Weber
1990	—	`conf`	Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Processing. DAGM-Symposium Reiner W. Hartenstein, Alexander G. Hirschbiel, Michael Riedmüller, Karin Schmidt, Michael Weber
1990	—	`conf`	The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration. ICPP (1) Reiner W. Hartenstein, Alexander G. Hirschbiel, Michael Weber
1990	C	`conf`	Xputer use in image processing and digital signal processing. VCIP Reiner W. Hartenstein, Alexander G. Hirschbiel, Karin Lemmert, Michael Riedmüller, Karin Schmidt, Michael Weber
1990	—	`conf`	Xputers: An Open Family of Non-Von Neumann Architectures. ARCS Reiner W. Hartenstein, Alexander G. Hirschbiel, Michael Weber
1990	—	`conf`	Xputers: very high throughput by innovative computing principles. Jerusalem Conference on Information Technology Reiner W. Hartenstein, Alexander G. Hirschbiel, Michael Weber
1989	J	`jnl`	Explicit fault modeling and hierarchical test pattern generation in the KARATE system. Microprocessing and Microprogramming Gerold Alfs, Reiner W. Hartenstein, Andrea Wodtko
1989	J	`jnl`	Synthesis of systolic architectures using the SYS Microprocessing and Microprogramming Reiner W. Hartenstein, Karin Lemmert, Michael Riedmüller
1988	J	`jnl`	A technology description method for generalized layout / circuit relations. Microprocess. Microprogramming Joachim Blödel, Reiner W. Hartenstein, Wolfgang Nebel, Michael Ryba
1988	—	`conf`	MLED - Ein Mehrebenen Graphik Editor für den VLSI-Entwurf. GI Jahrestagung (2) Reiner W. Hartenstein, K. W. Jörg, Udo Welters
1988	J	`jnl`	Microelectronics: VLSI design tools I. Microprocess. Microprogramming Reiner W. Hartenstein
1988	—	`conf`	Partitionierungsschemata für Rechnerstrukturen. GI Jahrestagung (2) Reiner W. Hartenstein, Michael Ryba
1988	A	`conf`	The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level Descriptions. ITC Gerold Affs, Reiner W. Hartenstein, Andrea Wodtko
1988	C	`conf`	The KARL/KARATE system - integrating functional test development into a CAD environment for VLSI. ICCD Gerold Alfs, Reiner W. Hartenstein, Andrea Wodtko
1987	J	`jnl`	A flexible architecture for image processing. Microprocess. Microprogramming Reiner W. Hartenstein, Alexander G. Hirschbiel, Michael Weber
1987	J	`jnl`	MLED: A multiple abstraction level graphical editor. Microprocess. Microprogramming Reiner W. Hartenstein, Udo Welters
1987	—	`conf`	Mehrebenenen-Graphik-Editor MLED als DBMS für VLSI-Simulation. Simulationstechnik Reiner W. Hartenstein, Udo Welters
1983	J	`jnl`	Silicon Compiler - Das aktuelle Schlagwort. Inform. Spektrum Reiner W. Hartenstein
1982	—	`conf`	Die "Neue Mikroelektronik" in der Informatik: Voraussetzungen und Auswirkungen. GI Jahrestagung Reiner W. Hartenstein
1982	J	`jnl`	KARL-II - eine Sprache zur Spezifikation beim Entwurf Kundenspezifischer Digitalbausteine. Angew. Inform. Reiner W. Hartenstein
1981	J	`jnl`	VLSI-Algorithmen - Das aktuelle Schlagwort. Inform. Spektrum Reiner W. Hartenstein
1980	—	`conf`	Ein Compiler für die Register Transfer-Sprache KARL-2. GI Jahrestagung Reiner W. Hartenstein, Peter Liell
1980	—	`conf`	Software-Zuverlässigkeit mit Rechnernetz-Baukästen verteilter Programmierung. Hardware für Software J. Dieckmann, Reiner W. Hartenstein, Werner Konrad
1980	J	`jnl`	VLSI-Bausteine in geringen Stückzahlen für Spezial-Anwendungen. Elektron. Rechenanlagen Reiner W. Hartenstein
1977	—	`book`	Fundamentals of Structured Hardware Design. Reiner W. Hartenstein
1974	—	`conf`	Konzepte der Mikroprogrammierung. ARCS Reiner W. Hartenstein
1974	J	`jnl`	Letter to membership from incoming chairman (CAN, Oct. 73). SIGARCH Comput. Archit. News Reiner W. Hartenstein
1974	A*	`conf`	Microprogramming concepts - a step towards structured hardware design. MICRO Reiner W. Hartenstein
1973	A*	`conf`	A microprogrammable display processor concept. MICRO Reiner W. Hartenstein, Klaus D. Mueller
1973	—	`conf`	Hierarchy of Interpreters for Modelling Complex Digital Systems. GI Jahrestagung Reiner W. Hartenstein
1973	A*	`conf`	Increasing Hardware Complexity - A Challenge to Computer Architecture Education. ISCA Reiner W. Hartenstein
1972	—	`conf`	Experimentiersystem für ein technisches Informatikpraktikum. GI Jahrestagung Reiner W. Hartenstein
1971	J	`jnl`	Synthese endlicher Automaten bei Problemen der Erkennung, Klassifikation und Informationsreduktion. J. Inf. Process. Cybern. Reiner W. Hartenstein
1970	J	`jnl`	Suchlistenstrukturen zur Darstellung gerichteter Graphen und deren Anwendung bei Synthese und Minimierung spezieller endlicher Automaten. Elektron. Rechenanlagen Reiner W. Hartenstein