Reiner Kolla

38 papers A* 2A 3B 5C 2Journal 10Unranked 13
YearRankTypeTitle / Venue / Authors
2017 — conf
MCGC: A Network Coding Approach for Reliable Large-scale Wireless Networks.
FAILSAFE@SenSys
Isabel Madeleine Runge, Reiner Kolla
2017 J jnl
TwoPhases: A transmission scheme to reduce the link width at deflection routing based Network-on-Chips.
J. Syst. Archit.
Armin Runge, Reiner Kolla
2016 C conf
A wearable 1-lead necklace ECG for continuous heart rate monitoring.
HealthCom
Aulia Arif Iskandar, Reiner Kolla, Klaus Schilling, Wolfram Völker
2016 — conf
An Alternating Transmission Scheme for Deflection Routing Based Network-on-Chips.
ARCS
Armin Runge, Reiner Kolla
2016 — conf
Consideration of the Flit Size for Deflection Routing based Network-on-Chips.
AISTECS@HiPEAC
Armin Runge, Reiner Kolla
2016 — conf
Using benes networks at fault-tolerant and deflection routing based network-on-chips.
NOCS
Armin Runge, Reiner Kolla
2011 C conf
Precise self-calibration of ultrasound based indoor localization systems.
IPIN
Armin Runge, Marcel Baunach, Reiner Kolla
2007 B conf
A Method for Self-Organizing Communication in WSN Based Localization Systems: HashSlot.
LCN
Marcel Baunach, Reiner Kolla, Clemens Muhlberger
2007 B conf
Beyond Theory: Development of a Real World Localization Application as Low Power WSN.
LCN
Marcel Baunach, Reiner Kolla, Clemens Muhlberger
2003 J jnl
Disproving the Perfect-Rate Property of Data-Flow Graphs Unfolded by the Least Common Multiple of the Number of Loop Registers.
IEEE Trans. Computers
Frank Wolz, Reiner Kolla
2002 B conf
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures.
FPL
Frank Wolz, Reiner Kolla
2001 B conf
Bubble Partitioning for LUT-Based Sequential Circuits.
FPL
Frank Wolz, Reiner Kolla
2000 B conf
A New Floorplanning Method for FPGA Architectural Research.
FPL
Frank Wolz, Reiner Kolla
2000 J jnl
Technology Binding.
Inform. Spektrum
Reiner Kolla
1999 A conf
Spanning Tree-based State Encoding for Low Power Dissipation.
DATE
Winfried Nöth, Reiner Kolla
1999 — conf
Splitting Double Precision FPUs for Single Precision Interval Arithmetic.
ARCS Workshops
Reiner Kolla, A. Vodopivec, Jürgen Wolff von Gudenberg
1998 A* conf
Boolean Matching for Large Libraries.
DAC
Uwe Hinsberger, Reiner Kolla
1998 — conf
PACE: Processor Architectures for Circuit Emulation.
IPPS/SPDP Workshops
Reiner Kolla, Oliver Springauf
1997 — conf
A parallel hybrid approach to hard optimization problems.
ARCS
Uwe Hinsberger, Reiner Kolla, Markus Wild
1997 A conf
Node normalization and decomposition in low power technology mapping.
ISLPED
Winfried Nöth, Reiner Kolla
1996 — conf
TROY: A Tree-Based Approach to Logic Synthesis and Technology Mapping.
Great Lakes Symposium on VLSI
Winfried Nöth, Uwe Hinsberger, Reiner Kolla
1995 — conf
Optimal technology mapping for single output cells.
Great Lakes Symposium on VLSI
Uwe Hinsberger, Reiner Kolla
1992 J jnl
A cell-based approach to performance optimization of fanout-free circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Uwe Hinsberger, Reiner Kolla
1992 — ch.
Performance Optimization of Combinational Circuits.
Informatik
Uwe Hinsberger, Reiner Kolla
1991 J jnl
The Virtual Feedback Problem in Hierarchical Representations of Combinational Circuits.
Acta Informatica
Reiner Kolla, Bernd Serf
1990 — conf
A dynamic programming approach to the power supply net sizing problem.
EURO-DAC
Reiner Kolla
1990 — conf
A graphical system for hierarchical specifications and checkups of VLSI circuits.
EURO-DAC
Bernd Becker, Thomas Burch, Günter Hotz, D. Kiel, Reiner Kolla, Paul Molitor, Hans-Georg Osthof, Gisela Pitsch, Uwe Sparmann
1990 — conf
Cell based performance optimization of combinational circuits.
EURO-DAC
Uwe Hinsberger, Reiner Kolla
1990 J jnl
Minimal Area Sizing of Power Supply Nets in VLSI Circuits.
J. Inf. Process. Cybern.
Reiner Kolla
1989 J jnl
A note on hierarchical layer-assignment.
Integr.
Reiner Kolla, Paul Molitor
1989 — book
Einführung in den VLSI-Entwurf.
Reiner Kolla, Paul Molitor, Hans-Georg Osthof
1988 A conf
On the Construction of Optimal Time Adders (Extended Abstract).
STACS
Bernd Becker, Reiner Kolla
1987 A* conf
Hierarchical Design Based on a Calculus of Nets.
DAC
Bernd Becker, Günter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof
1987 — —
Spezifikation und Expansion logisch-topologischer Netze.
Reiner Kolla
1986 J jnl
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I.
Inform. Forsch. Entwickl.
Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor
1986 J jnl
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II.
Inform. Forsch. Entwickl.
Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor
1986 — conf
On Network Algebras and Recursive Equations.
Graph-Grammars and Their Application to Computer Science
Günter Hotz, Reiner Kolla, Paul Molitor
1983 J jnl
Where-Oblivious is not Sufficient.
Inf. Process. Lett.
Reiner Kolla