Reetuparna Das

90 papers A* 43A 4B 6C 1Misc 1Journal 24Unranked 10

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Characterizing Adaptive Mesh Refinement on Heterogeneous Platforms with Parthenon-VIBE. IISWC Akash Poptani, Alireza Khadem, Scott A. Mahlke, Jonah M. Miller, Joshua C. Dolence, Galen M. Shipman, Reetuparna Das
2025	J	`jnl`	Characterizing Adaptive Mesh Refinement on Heterogeneous Platforms with Parthenon-VIBE. CoRR Akash Poptani, Alireza Khadem, Scott A. Mahlke, Jonah M. Miller, Joshua C. Dolence, Reetuparna Das
2025	J	`jnl`	DX100: A Programmable Data Access Accelerator for Indirection. CoRR Alireza Khadem, Kamalavasan Kamalakkannan, Zhenyan Zhu, Akash Poptani, Yufeng Gu, Jered Benjamin Dominguez-Trujillo, Nishil Talati, Daichi Fujiki, Scott A. Mahlke, Galen M. Shipman, Reetuparna Das
2025	A*	`conf`	DX100: Programmable Data Access Accelerator for Indirection. ISCA Alireza Khadem, Kamalavasan Kamalakkannan, Zhenyan Zhu, Akash Poptani, Yufeng Gu, Jered Benjamin Dominguez-Trujillo, Nishil Talati, Daichi Fujiki, Scott A. Mahlke, Galen M. Shipman, Reetuparna Das
2025	J	`jnl`	GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis. Commun. ACM Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Mohammad Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2025	A*	`conf`	Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing. HPCA Alireza Khadem, Daichi Fujiki, Hilbert Chen, Yufeng Gu, Nishil Talati, Scott A. Mahlke, Reetuparna Das
2025	J	`jnl`	Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing. CoRR Alireza Khadem, Daichi Fujiki, Hilbert Chen, Yufeng Gu, Nishil Talati, Scott A. Mahlke, Reetuparna Das
2025	—	`conf`	PIM Is All You Need: A CXL-Enabled GPU-Free System for Large Language Model Inference. ASPLOS (2) Yufeng Gu, Alireza Khadem, Sumanth Umesh, Ning Liang, Xavier Servot, Onur Mutlu, Ravi R. Iyer, Reetuparna Das
2025	J	`jnl`	PIM Is All You Need: A CXL-Enabled GPU-Free System for Large Language Model Inference. CoRR Yufeng Gu, Alireza Khadem, Sumanth Umesh, Ning Liang, Xavier Servot, Onur Mutlu, Ravi R. Iyer, Reetuparna Das
2025	—	`conf`	PangenomicsBench: A Benchmark Suite and Characterization of Pangenomics. IISWC Noah Kaplan, Jan-Niklas Schmelzle, Yufeng Gu, Erik Garrison, Christopher Batten, Reetuparna Das
2024	A*	`conf`	Duet: A Collaborative User Driven Recommendation System for Edge Devices. DAC Vidushi Goyal, Valeria Bertacco, Reetuparna Das
2024	J	`jnl`	Systems Challenges and Opportunities for Genomics. Computer Reetuparna Das, Satish Narayanasamy
2023	J	`jnl`	BitSET: Bit-Serial Early Termination for Computation Reduction in Convolutional Neural Networks. ACM Trans. Embed. Comput. Syst. Yunjie Pan, Jiecao Yu, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke
2023	J	`jnl`	Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks. IEEE Trans. Computers Charles Eckert, Arun Subramaniyan, Xiaowei Wang, Charles Augustine, Ravishankar Iyer, Reetuparna Das
2023	A*	`conf`	GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis. ISCA Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2023	—	`conf`	Vector-Processing for Mobile Devices: Benchmark and Analysis. IISWC Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das
2023	J	`jnl`	Vector-Processing for Mobile Devices: Benchmark and Analysis. CoRR Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das
2023	J	`jnl`	nPoRe: n-polymer realigner for improved pileup-based variant calling. BMC Bioinform. Timothy Dunn, David T. Blaauw, Reetuparna Das, Satish Narayanasamy
2022	J	`jnl`	Hardware-friendly User-specific Machine Learning for Edge Devices. ACM Trans. Embed. Comput. Syst. Vidushi Goyal, Reetuparna Das, Valeria Bertacco
2022	A*	`conf`	Multi-Layer In-Memory Processing. MICRO Daichi Fujiki, Alireza Khadem, Scott A. Mahlke, Reetuparna Das
2022	J	`jnl`	Special Issue on In-Memory Computing. IEEE Micro Reetuparna Das
2021	J	`jnl`	A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array. IEEE J. Solid State Circuits Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw
2021	A*	`conf`	Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees. ISCA Arun Subramaniyan, Jack Wadden, Kush Goliya, Nathan Ozog, Xiao Wu, Satish Narayanasamy, David T. Blaauw, Reetuparna Das
2021	—	`conf`	Cache Compression with Efficient in-SRAM Data Comparison. NAS Xiaowei Wang, Charles Augustine, Eriko Nurvitadhi, Ravi R. Iyer, Li Zhao, Reetuparna Das
2021	Misc	`conf`	Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. FCCM Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das
2021	B	`conf`	GenomicsBench: A Benchmark Suite for Genomics. ISPASS Arun Subramaniyan, Yufeng Gu, Timothy Dunn, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2021	—	`book`	In-/Near-Memory Computing Daichi Fujiki, Xiaowei Wang, Arun Subramaniyan, Reetuparna Das
2021	A*	`conf`	MyML: User-Driven Machine Learning. DAC Vidushi Goyal, Valeria Bertacco, Reetuparna Das
2021	A*	`conf`	SquiggleFilter: An Accelerator for Portable Virus Detection. MICRO Timothy Dunn, Harisankar Sadasivan, Jack Wadden, Kush Goliya, Kuan-Yu Chen, David T. Blaauw, Reetuparna Das, Satish Narayanasamy
2020	—	`conf`	A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array. CICC Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw
2020	J	`jnl`	A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing. IEEE J. Solid State Circuits Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester
2020	—	`conf`	MARTINI: Memory Access Traces to Detect Attacks. CCSW Yujun Qin, Samuel Gonzalez, Kevin Angstadt, Xiaowei Wang, Stephanie Forrest, Reetuparna Das, Kevin Leach, Westley Weimer
2020	A	`conf`	Neksus: An Interconnect for Heterogeneous System-In-Package Architectures. IPDPS Vidushi Goyal, Xiaowei Wang, Valeria Bertacco, Reetuparna Das
2020	A*	`conf`	SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space. MICRO Daichi Fujiki, Shunhao Wu, Nathan Ozog, Kush Goliya, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2020	A*	`conf`	Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning. DAC Vidushi Goyal, Valeria Bertacco, Reetuparna Das
2019	—	`conf`	A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration. ISSCC Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester
2019	A*	`conf`	Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks. HPCA Xiaowei Wang, Jiecao Yu, Charles Augustine, Ravi R. Iyer, Reetuparna Das
2019	A*	`conf`	Duality cache for data parallel acceleration. ISCA Daichi Fujiki, Scott A. Mahlke, Reetuparna Das
2019	J	`jnl`	Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. IEEE Micro Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Dennis Sylvester, David T. Blaauw, Reetuparna Das, Ravi R. Iyer
2019	J	`jnl`	TF-Net: Deploying Sub-Byte Deep Neural Networks on Microcontrollers. ACM Trans. Embed. Comput. Syst. Jiecao Yu, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke
2018	A*	`conf`	ASPEN: A Scalable In-SRAM Architecture for Pushdown Automata. MICRO Kevin Angstadt, Arun Subramaniyan, Elaheh Sadredini, Reza Rahimi, Kevin Skadron, Westley Weimer, Reetuparna Das
2018	A*	`conf`	GenAx: A Genome Sequencing Accelerator. ISCA Daichi Fujiki, Arun Subramaniyan, Tianjun Zhang, Yu Zeng, Reetuparna Das, David T. Blaauw, Satish Narayanasamy
2018	A*	`conf`	In-Memory Data Parallel Processor. ASPLOS Daichi Fujiki, Scott A. Mahlke, Reetuparna Das
2018	A*	`conf`	Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. ISCA Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi R. Iyer, Dennis Sylvester, David T. Blaauw, Reetuparna Das
2018	J	`jnl`	Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. CoRR Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi R. Iyer, Dennis Sylvester, David T. Blaauw, Reetuparna Das
2017	J	`jnl`	Blurring the Lines between Memory and Computation. IEEE Micro Reetuparna Das
2017	B	`conf`	Cache Automaton: Repurposing Caches for Automata Processing. PACT Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das
2017	A*	`conf`	Cache automaton. MICRO Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das
2017	A*	`conf`	Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors. HPCA Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Reetuparna Das, Todd M. Austin
2017	A*	`conf`	Compute Caches. HPCA Shaizeen Aga, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David T. Blaauw, Reetuparna Das
2017	B	`conf`	In-memory Data Flow Processor. PACT Daichi Fujiki, Scott A. Mahlke, Reetuparna Das
2017	A*	`conf`	Mirage cores: the illusion of many out-of-order cores using in-order hardware. MICRO Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke
2017	A*	`conf`	Parallel Automata Processor. ISCA Arun Subramaniyan, Reetuparna Das
2017	A*	`conf`	Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism. ISCA Jiecao Yu, Andrew Lukefahr, David J. Palframan, Ganesh S. Dasika, Reetuparna Das, Scott A. Mahlke
2016	J	`jnl`	A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate. Parallel Comput. Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
2016	A*	`conf`	ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks. ASPLOS Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Rui Qiao, Reetuparna Das, Matthew Hicks, Yossi Oren, Todd M. Austin
2016	J	`jnl`	Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing. CoRR Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
2016	J	`jnl`	Exploring Fine-Grained Heterogeneity with Composite Cores. IEEE Trans. Computers Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke
2016	A	`conf`	Exploring specialized near-memory processing for data intensive operations. DATE Salessawi Ferede Yitbarek, Tao Yang, Reetuparna Das, Todd M. Austin
2015	A*	`conf`	DynaMOS: dynamic schedule migration for heterogeneous cores. MICRO Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke
2015	A	`conf`	Getting in control of your control flow with control-data isolation. CGO William Arthur, Ben Mehne, Reetuparna Das, Todd M. Austin
2015	A*	`conf`	Locking down insecure indirection with hardware-based control-data isolation. MICRO William Arthur, Sahil Madeka, Reetuparna Das, Todd M. Austin
2014	C	`conf`	Design and Evaluation of Hierarchical Rings with Deflection Routing. SBAC-PAD Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
2014	B	`conf`	Heterogeneous microarchitectures trump voltage scaling for low-power cores. PACT Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke
2014	A*	`conf`	Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration. MICRO Supreet Jeloka, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, David T. Blaauw
2014	A*	`conf`	Power-Aware NoCs through Routing and Topology Reconfiguration. DAC Ritesh Parikh, Reetuparna Das, Valeria Bertacco
2014	A*	`conf`	Quality-of-Service for a High-Radix Switch. DAC Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David T. Blaauw, Ronald G. Dreslinski, Reetuparna Das, Trevor N. Mudge
2014	A*	`conf`	VIX: Virtual Input Crossbar for Efficient Switch Allocation. DAC Supriya Rao, Supreet Jeloka, Reetuparna Das, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge
2013	A*	`conf`	Application-to-core mapping policies to reduce memory system interference in multi-core systems. HPCA Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi
2013	A*	`conf`	Catnap: energy proportional multiple network-on-chip. ISCA Reetuparna Das, Satish Narayanasamy, Sudhir Satpathy, Ronald G. Dreslinski
2013	A*	`conf`	Scaling towards kilo-core processors with asymmetric high-radix topologies. HPCA Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge
2013	A*	`conf`	Trace based phase prediction for tightly-coupled heterogeneous cores. MICRO Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke
2012	B	`conf`	Application-to-core mapping policies to reduce memory interference in multi-core systems. PACT Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, Mani Azimi
2012	A*	`conf`	Composite Cores: Pushing Heterogeneity Into a Core. MICRO Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke
2012	A*	`conf`	High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service. DAC Sudhir Satpathy, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2012	—	`conf`	Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems. Hot Chips Symposium Ronald G. Dreslinski, Korey Sewell, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge
2012	J	`jnl`	Swizzle-Switch Networks for Many-Core Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. Korey Sewell, Ronald G. Dreslinski, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge
2012	B	`conf`	XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems. PACT Ronald G. Dreslinski, Thomas Manville, Korey Sewell, Reetuparna Das, Nathaniel Ross Pinckney, Sudhir Satpathy, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge
2011	J	`jnl`	Aérgia: A Network-on-Chip Exploiting Packet Latency Slack. IEEE Micro Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das
2011	J	`jnl`	RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distributed Comput. Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
2010	A*	`conf`	Aérgia: exploiting packet latency slack in on-chip networks. ISCA Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das
2010	A*	`conf`	Cost-driven 3D integration with interconnect layers. DAC Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li
2009	A*	`conf`	A case for dynamic frequency tuning in on-chip networks. MICRO Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
2009	A	`conf`	A case for integrated processor-cache partitioning in chip multiprocessors. SC Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir
2009	A*	`conf`	Application-aware prioritization mechanisms for on-chip networks. MICRO Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das
2009	A*	`conf`	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
2008	A*	`conf`	MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
2008	A*	`conf`	Performance and power optimization through data compression in Network-on-Chip architectures. HPCA Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer, Mazin S. Yousif, Chita R. Das
2007	A*	`conf`	A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
2007	—	`conf`	Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects. Hot Interconnects Dongkook Park, Reetuparna Das, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Ravishankar R. Iyer, Chita R. Das