Raymond Hoare

17 papers A 4Misc 1Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2007 J jnl
An automated, FPGA-based reconfigurable, low-power RFID tag.
Microprocess. Microsystems
Alex K. Jones, Raymond Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle
2006 J jnl
Reducing power while increasing performance with supercisc.
ACM Trans. Embed. Comput. Syst.
Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster
2006 J jnl
Speech Silicon: An FPGA Architecture for Real-Time Hidden Markov-Model-Based Speech Recognition.
EURASIP J. Embed. Syst.
Jeffrey William Schuster, Kshitij Gupta, Raymond Hoare, Alex K. Jones
2006 J jnl
Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).
Microprocess. Microsystems
Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones
2005 A conf
An FPGA-based VLIW processor with custom hardware execution.
FPGA
Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster
2005 A conf
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism.
IPDPS
Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster
2005 Misc conf
Optimizing Technology Mapping for FPGAs Using CAMs.
FCCM
Joshua M. Lucas, Raymond Hoare, Alex K. Jones
2004 — conf
A 64-way VLIW/SIMD FPGA architecture and design flow.
ICECS
Alex K. Jones, Raymond Hoare, Ivan S. Kourtev, Joshua Fazekas, Dara Kusic, John Foster, Sedric Boddie, Ahmed Muaydh
2004 A conf
An 88-Way Multiprocessor within an FPGA with Customizable Instructions.
IPDPS
Raymond Hoare, Shen Chih Tung, Katrina Werger
2003 — conf
Combining Mentor Graphics? HDL Designer FPGA Flow with a Reconfigurable System on a Programmable Chip, Educational Opportunity or Insanity?
MSE
Raymond Hoare, Shen Chih Tung
2002 A conf
An SoC Solution for Massive Parallel Processing.
IPDPS
David Reed, Raymond Hoare
2002 J jnl
Cross-institutional assessment: Development and implementation of the On-line Student Survey System.
Comput. Appl. Eng. Educ.
Raymond Hoare, Mary Besterfield-Sacre, Dan Ertman, Jessica Gerchak, Troy A. Johnson, Robert Shields, Larry J. Shuman
2000 — conf
ClusterNet: An Object-Oriented Cluster Network.
IPDPS Workshops
Raymond Hoare
1998 — conf
A Case for Aggregate Networks.
IPPS/SPDP
Raymond Hoare, Henry G. Dietz
1997 — conf
VLIW Across Multiple Superscalar Processors on a Single Chip.
IEEE PACT
Soohong P. Kim, Raymond Hoare, Henry G. Dietz
1996 — conf
A Fine-Grain Parallel Architecture Based on Barrier Synchronization.
ICPP, Vol. 1
Henry G. Dietz, Raymond Hoare, Timothy Mattox
1996 — conf
Bitwise aggregate networks.
SPDP
Raymond Hoare, Henry G. Dietz, Timothy Mattox, Soohong P. Kim