Raviteja Theertham

11 papers C 1Journal 6Unranked 4

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors. ISSCC Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Qingnan Yu, Zhao Li, Zeynep Lulec, Konstantinos Vasilakopoulos, Prawal Shrestha, Donald Paterson, Raviteja Theertham, Aseer Chowdhury
2024	J	`jnl`	A -90-dBFS-IM IEEE J. Solid State Circuits Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Prawal Shrestha, Zhao Li, Sevil Zeynep Lulec, Konstantinos Vasilakopoulos, Raviteja Theertham, Donald Paterson, Qingnan Yu, Aseer Chowdhury
2023	—	`conf`	A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs. CICC Sharvil Patil, Raviteja Theertham, Hajime Shibata, Victor Kozlov, Asha Ganesan, Efram Burlingame, Zhao Li, Rama Thakar, Qianqian Zhang, Yue Yin, Aathreya S. Bhat
2022	—	`conf`	A 0.37mm CICC Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun
2022	J	`jnl`	Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback. IEEE Trans. Circuits Syst. II Express Briefs Raviteja Theertham, Shanthi Pavan
2022	J	`jnl`	Design of High-Resolution Continuous-Time Delta-Sigma Data Converters With Dual Return-to-Open DACs. IEEE J. Solid State Circuits Raviteja Theertham, Satya Narayana Ganta, Shanthi Pavan
2020	J	`jnl`	Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density. IEEE J. Solid State Circuits Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan
2020	C	`conf`	Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators. ISCAS Raviteja Theertham, Shanthi Pavan
2019	—	`conf`	A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth. VLSI Circuits Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan
2019	J	`jnl`	Improved Offline Calibration of DAC Mismatch Errors in Delta-Sigma Data Converters. IEEE Trans. Circuits Syst. II Express Briefs Shanthi Pavan, Raviteja Theertham
2019	J	`jnl`	Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Raviteja Theertham, Shanthi Pavan