Ravindranath Naiknaware

11 papers A 2C 1Misc 1Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2004 J jnl
Process-insensitive low-power design of switched-capacitor integrators.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ravindranath Naiknaware, Terri S. Fiez
2000 — conf
142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS process.
CICC
Ravindranath Naiknaware, Terri S. Fiez
1999 J jnl
Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations.
IEEE J. Solid State Circuits
Ravindranath Naiknaware, Terri S. Fiez
1999 J jnl
Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations.
IEEE J. Solid State Circuits
Ravindranath Naiknaware, Terri S. Fiez
1999 — conf
Switched-capacitor integrator design optimizing for power and process variations.
ISCAS (2)
Ravindranath Naiknaware, Terri S. Fiez
1999 — conf
Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer.
ISCAS (2)
Ravindranath Naiknaware, Terri S. Fiez
1998 A conf
CMOS analog circuit stack generation with matching constraints.
ICCAD
Ravindranath Naiknaware, Terri S. Fiez
1998 — conf
Schematic driven module generation for analog circuits with performance optimization and matching considerations.
CICC
Ravindranath Naiknaware, Terri S. Fiez
1993 C conf
Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment.
ICCD
Ravindranath Naiknaware
1993 Misc conf
Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach.
VLSI Design
Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin
1993 A conf
Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation.
ITC
Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa