Raphael Polig

25 papers A* 1A 2B 7Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2024 A conf
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach.
DATE
Christian Pilato, Subhadeep Banik, Jakub Beránek, Fabien Brocheton, Jerónimo Castrillón, Riccardo Cevasco, Radim Cmar, Serena Curzel, Fabrizio Ferrandi, Karl F. A. Friebel, Antonella Galizia, Matteo Grasso, Paulo Silva, Jan Martinovic, Gianluca Palermo, Michele Paolino, Andrea Parodi, Antonio Parodi, Fabio Pintus, Raphael Polig, David Poulet, Francesco Regazzoni, Burkhard Ringlein, Roberto Rocco, Katerina Slaninová, Tom Slooff, Stephanie Soldavini, Felix Suchert, Mattia Tibaldi, Beat Weiss, Christoph Hagleitner
2024 J jnl
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach.
CoRR
Christian Pilato, Subhadeep Banik, Jakub Beránek, Fabien Brocheton, Jerónimo Castrillón, Riccardo Cevasco, Radim Cmar, Serena Curzel, Fabrizio Ferrandi, Karl F. A. Friebel, Antonella Galizia, Matteo Grasso, Paulo Silva, Jan Martinovic, Gianluca Palermo, Michele Paolino, Andrea Parodi, Antonio Parodi, Fabio Pintus, Raphael Polig, David Poulet, Francesco Regazzoni, Burkhard Ringlein, Roberto Rocco, Katerina Slaninová, Tom Slooff, Stephanie Soldavini, Felix Suchert, Mattia Tibaldi, Beat Weiss, Christoph Hagleitner
2021 B conf
Acceleration-as-a-µService: A Cloud-native Monte-Carlo Option Pricing Engine on CPUs, GPUs and Disaggregated FPGAs.
CLOUD
Dionysios Diamantopoulos, Raphael Polig, Burkhard Ringlein, Mitra Purandare, Beat Weiss, Christoph Hagleitner, Mark A. Lantz, François Abel
2021 J jnl
Acceleration-as-a-μService: A Cloud-native Monte-Carlo Option Pricing Engine on CPUs, GPUs and Disaggregated FPGAs.
CoRR
Dionysios Diamantopoulos, Raphael Polig, Burkhard Ringlein, Mitra Purandare, Beat Weiss, Christoph Hagleitner, Mark A. Lantz, François Abel
2020 J jnl
FPGA Accelerated Analysis of Boolean Gene Regulatory Networks.
IEEE ACM Trans. Comput. Biol. Bioinform.
Matteo Manica, Raphael Polig, Mitra Purandare, Roland Mathis, Christoph Hagleitner, María Rodríguez Martínez
2018 J jnl
A hardware compilation framework for text analytics queries.
J. Parallel Distributed Comput.
Raphael Polig, Kubilay Atasu, Heiner Giefers, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee
2018 J jnl
Giving Text Analytics a Boost.
CoRR
Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Eva Sitaridi, Huaiyu Zhu
2017 B conf
Accelerated analysis of Boolean gene regulatory networks.
FPL
Mitra Purandare, Raphael Polig, Christoph Hagleitner
2017 A* conf
Formal Techniques for Effective Co-verification of Hardware/Software Co-designs.
DAC
Rajdeep Mukherjee, Mitra Purandare, Raphael Polig, Daniel Kroening
2016 J jnl
A fast, hybrid, power-efficient high-precision solver for large linear systems based on low-precision hardware.
Sustain. Comput. Informatics Syst.
Christoph M. Angerer, Raphael Polig, D. Zegarac, Heiner Giefers, Christoph Hagleitner, Costas Bekas, Alessandro Curioni
2016 B conf
Annotation-based finite-state transducers on reconfigurable devices.
FPL
Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama
2016 B conf
Energy-efficient stochastic matrix function estimator for graph analytics on FPGA.
FPL
Heiner Giefers, Peter W. J. Staar, Raphael Polig
2016 J jnl
Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT.
J. Signal Process. Syst.
Heiner Giefers, Raphael Polig, Christoph Hagleitner
2016 — conf
Network-attached FPGAs for data center applications.
FPT
Jagath Weerasinghe, Raphael Polig, François Abel, Christoph Hagleitner
2015 — conf
A soft-core processor array for relational operators.
ASAP
Raphael Polig, Heiner Giefers, Walter Stechele
2015 A conf
Accelerating arithmetic kernels with coherent attached FPGA coprocessors.
DATE
Heiner Giefers, Raphael Polig, Christoph Hagleitner
2015 — —
Text Analytics on Reconfigurable Platforms.
Raphael Polig
2014 — conf
Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system.
ASAP
Heiner Giefers, Raphael Polig, Christoph Hagleitner
2014 B conf
Compiling text analytics queries to FPGAs.
FPL
Raphael Polig, Kubilay Atasu, Heiner Giefers, Laura Chiticariu
2014 J jnl
Giving Text Analytics a Boost.
IEEE Micro
Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Huaiyu Zhu, Eva Sitaridi
2014 — conf
Hardware-accelerated text analytics.
Hot Chips Symposium
Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee
2013 — conf
A high-speed and large-scale dictionary matching engine for Information Extraction systems.
ASAP
Kanak Agarwal, Raphael Polig
2013 J jnl
Exploring the design space of programmable regular expression matching accelerators.
J. Syst. Archit.
Kubilay Atasu, Raphael Polig, Jonathan Rohrer, Christoph Hagleitner
2013 B conf
Hardware-accelerated regular expression matching for high-throughput text analytics.
FPL
Kubilay Atasu, Raphael Polig, Christoph Hagleitner, Frederick R. Reiss
2013 B conf
Token-based dictionary pattern matching for text analytics.
FPL
Raphael Polig, Kubilay Atasu, Christoph Hagleitner