Ranjani Narayan

53 papers B 1C 3Misc 13Journal 15Unranked 21
YearRankTypeTitle / Venue / Authors
2019 Misc conf
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design.
VLSID
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
2019 Misc conf
Applying Modified Householder Transform to Kalman Filter.
VLSID
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
2018 — conf
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design.
ARC
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2018 J jnl
Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design.
CoRR
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2018 J jnl
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization.
CoRR
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
2018 J jnl
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization.
IEEE Trans. Parallel Distributed Syst.
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2017 J jnl
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design.
Parallel Process. Lett.
Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2017 J jnl
Energy aware synthesis of application kernels through composition of data-paths on a CGRA.
Integr.
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
2017 Misc conf
REDEFINE
CASES
Kavitha T. Madhu, Tarun Singla, S. K. Nandy, Ranjani Narayan, François Neumann, Philippe Baufreton
2016 J jnl
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design.
CoRR
Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2016 J jnl
Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design.
CoRR
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2016 Misc conf
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation.
VLSID
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2016 J jnl
Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization.
CoRR
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2016 Misc conf
Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic.
VLSID
Farhad Merchant, Nimash Choudhary, S. K. Nandy, Ranjani Narayan
2016 — conf
Flexible resource allocation and management for application graphs on ReNÉ MPSoC.
PARMA-DITAM@HiPEAC
Kavitha T. Madhu, Anuj Rao, Saptarsi Das, Madhava Krishna C., S. K. Nandy, Ranjani Narayan
2016 J jnl
REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores.
IEEE Trans. Parallel Distributed Syst.
Gopinath Mahale, Hamsika Mahale, S. K. Nandy, Ranjani Narayan
2016 Misc conf
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels.
VLSID
Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan
2016 Misc conf
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks.
VLSID
Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan
2015 Misc conf
A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks.
VLSID
Mahnaz Mohammadi, Nitin Satpute, Rohit Ronge, Jayesh R. Chandiramani, S. K. Nandy, Aamir Raihan, Tanmay Verma, Ranjani Narayan, Sukumar Bhattacharya
2015 — conf
A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address.
SoCC
Alexander Fell, S. K. Nandy, Ranjani Narayan
2015 — conf
Compiling HPC Kernels for the REDEFINE CGRA.
HPCC/CSS/ICESS
Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2015 — conf
Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array.
iNIS
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
2015 Misc conf
Hardware Solution for Real-Time Face Recognition.
VLSID
Gopinath Mahale, Hamsika Mahale, Arnav Goel, S. K. Nandy, S. Bhattacharya, Ranjani Narayan
2015 Misc conf
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations.
VLSID
Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2015 J jnl
Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat.
Circuits Syst. Signal Process.
Arnab Kumar Biswas, S. K. Nandy, Ranjani Narayan
2015 J jnl
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture.
J. Low Power Electron.
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2014 J jnl
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths.
J. Syst. Archit.
Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan
2014 — conf
Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs.
ICSAMOS
Mahesh Mahadurkar, Farhad Merchant, Arka Maity, Kapil Vatwani, Ishan Munje, Nandhini Gopalan, S. K. Nandy, Ranjani Narayan
2014 Misc conf
Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR).
VLSID
Farhad Merchant, Anupam Chattopadhyay, Ganesh Garga, S. K. Nandy, Ranjani Narayan, Nandhini Gopalan
2014 — conf
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems.
ISED
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2014 — conf
Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath.
ICSAMOS
Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C., Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2013 C conf
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit.
ISCAS
S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan
2011 C conf
A Method for Flexible Reduction over Binary Fields using a Field Multiplier.
SECRYPT
Saptarsi Das, Keshavan Varadarajan, Ganesh Garga, Rajdeep Mondal, Ranjani Narayan, S. K. Nandy
2011 — conf
Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields.
ICETE (Selected Papers)
Saptarsi Das, Ranjani Narayan, Soumitra Kumar Nandy
2011 J jnl
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture.
IPSJ Trans. Syst. LSI Des. Methodol.
Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan, Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani Narayan
2011 — conf
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture.
ARC
Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan
2010 — conf
Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform.
ISVLSI
Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2010 — conf
Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform.
ICSAMOS
Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2010 — conf
Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture.
ICSAMOS
N. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2010 Misc conf
Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE.
CASES
Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita
2009 — conf
An Input Triggered Polymorphic ASIC for H.264 Decoding.
ASAP
Adarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, Sreeramula Sankaraiah, Sravanthi Mantha, S. K. Nandy, Ranjani Narayan
2009 — conf
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures.
ARC
Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan
2009 — conf
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT.
SoCC
Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
2009 J jnl
REDEFINE: Runtime reconfigurable polymorphic ASIC.
ACM Trans. Embed. Comput. Syst.
Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan
2009 Misc conf
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.
CASES
Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
2008 — conf
Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders.
ASAP
Adarsha Rao, Mythri Alle, S. K. Nandy, Ranjani Narayan
2008 — conf
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.
ASAP
Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan
2008 — conf
Synthesis of application accelerators on Runtime Reconfigurable Hardware.
ASAP
Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan
2007 B conf
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.
FPL
A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2006 C conf
Framework for Enabling Highly Available Distributed Applications for Utility Computing.
ISPA
J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan
2005 — conf
A Framework for QoS Adaptive Grid Meta Scheduling.
DEXA Workshops
K. C. Nainwal, J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan
1993 — conf
A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array.
ICPP (3)
S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan
1990 J jnl
Performance analysis of a multiprocessor machine based on data flow principles.
Microprocessing and Microprogramming
Ranjani Narayan, V. Rajaraman