Rangharajan Venkatesan

56 papers A* 11A 12B 2Journal 22Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	31.9 Alpha-Vision: A Real-Time Always-on Vision Processor with 787µs Face Detection Latency in <5mW. ISSCC Ben Keller, Rangharajan Venkatesan, Steve Dai, Jason Clemons, Matthew Fojtik, Muya Chang, Thierry Tambe, Nathaniel Ross Pinckney, Stephen G. Tell, Qijing Huang, Shalini De Mello, Brucek Khailany
2025	J	`jnl`	FGMP: Fine-Grained Mixed-Precision Weight and Activation Quantization for Hardware-Accelerated LLM Inference. CoRR Coleman Hooper, Charbel Sakr, Ben Keller, Rangharajan Venkatesan, Kurt Keutzer, Yakun Sophia Shao, Brucek Khailany
2025	A*	`conf`	SQ-DM: Accelerating Diffusion Models with Aggressive Quantization and Temporal Sparsity. DAC Zichen Fan, Steve Dai, Rangharajan Venkatesan, Dennis Sylvester, Brucek Khailany
2025	J	`jnl`	SQ-DM: Accelerating Diffusion Models with Aggressive Quantization and Temporal Sparsity. CoRR Zichen Fan, Steve Dai, Rangharajan Venkatesan, Dennis Sylvester, Brucek Khailany
2025	J	`jnl`	ThinKV: Thought-Adaptive KV Cache Compression for Efficient Reasoning Models. CoRR Akshat Ramachandran, Marina Neseem, Charbel Sakr, Rangharajan Venkatesan, Brucek Khailany, Tushar Krishna
2024	B	`conf`	Vision Transformer Computation and Resilience for Dynamic Inference. ISPASS Kavya Sreedhar, Jason Clemons, Rangharajan Venkatesan, Stephen W. Keckler, Mark Horowitz
2023	J	`jnl`	A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. IEEE J. Solid State Circuits Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany
2023	A*	`conf`	Efficient Transformer Inference with Statically Structured Sparse Attention. DAC Steve Dai, Hasan Genc, Rangharajan Venkatesan, Brucek Khailany
2022	—	`conf`	A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. VLSI Technology and Circuits Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany
2022	J	`jnl`	Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications. CoRR Kavya Sreedhar, Jason Clemons, Rangharajan Venkatesan, Stephen W. Keckler, Mark Horowitz
2022	J	`jnl`	Fair and Comprehensive Benchmarking of Machine Learning Processing Chips. IEEE Des. Test Geoffrey W. Burr, Sukhwan Lim, Boris Murmann, Rangharajan Venkatesan, Marian Verhelst
2022	J	`jnl`	LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update. IEEE Trans. Computers Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Fayez Ali, Ming-Yu Liu, Brucek Khailany, William J. Dally, Anima Anandkumar
2022	A*	`conf`	Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. ICML Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
2022	J	`jnl`	Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. CoRR Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
2021	A	`conf`	IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs. ICCAD Nathaniel Ross Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany
2021	J	`jnl`	Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update. CoRR Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Ming-Yu Liu, Brucek Khailany, Bill Dally, Anima Anandkumar
2021	—	`conf`	Session 3 Overview: Highlighted Chip Releases: Modern Digital SoCs Invited Papers. ISSCC Thomas Burd, Rangharajan Venkatesan, Dennis Sylvester
2021	J	`jnl`	Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
2021	A*	`conf`	Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. DAC Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
2021	J	`jnl`	Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. CoRR Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
2021	—	`conf`	VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. MLSys Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William J. Dally, Brucek Khailany
2021	J	`jnl`	VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. CoRR Steve Dai, Rangharajan Venkatesan, Haoxing Ren, Brian Zimmer, William J. Dally, Brucek Khailany
2021	J	`jnl`	Verifying High-Level Latency-Insensitive Designs with Formal Model Checking. CoRR Steve Dai, Alicia Klinefelter, Haoxing Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Ross Pinckney, Brucek Khailany
2020	J	`jnl`	A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2020	J	`jnl`	Accelerating Chip Design With Machine Learning. IEEE Micro Brucek Khailany, Haoxing Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William J. Dally
2019	—	`conf`	A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2019	—	`conf`	A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2019	A*	`conf`	Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. DAC Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray
2019	A*	`conf`	Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. ASPLOS Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer
2019	A	`conf`	MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany
2019	A*	`conf`	Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
2019	B	`conf`	Timeloop: A Systematic Approach to DNN Accelerator Evaluation. ISPASS Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer
2018	A*	`conf`	A modular digital VLSI flow for high-productivity SoC design. DAC Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer
2017	A*	`conf`	SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. ISCA Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
2017	J	`jnl`	SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. CoRR Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
2017	A	`conf`	STAxCache: An approximate, energy efficient STT-MRAM cache. DATE Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
2016	A*	`conf`	A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications. DAC Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Stephen W. Keckler
2016	J	`jnl`	Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes. ACM J. Emerg. Technol. Comput. Syst. A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
2016	J	`jnl`	Cache Design with Domain Wall Memory. IEEE Trans. Computers Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
2016	J	`jnl`	Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches. IEEE Trans. Very Large Scale Integr. Syst. Xuanyao Fong, Rangharajan Venkatesan, Dongsoo Lee, Anand Raghunathan, Kaushik Roy
2016	J	`jnl`	Emulation-Based Analysis of System-on-Chip Performance Under Variations. IEEE Trans. Very Large Scale Integr. Syst. Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey
2016	J	`jnl`	Spin-Transfer Torque Memories: Devices, Circuits, and Systems. Proc. IEEE Xuanyao Fong, Yusung Kim, Rangharajan Venkatesan, Sri Harsha Choday, Anand Raghunathan, Kaushik Roy
2015	A	`conf`	Asymmetric underlapped FinFET based robust SRAM design at 7nm node. DATE A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
2015	A	`conf`	DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s. DATE Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan
2015	J	`jnl`	Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage. ACM J. Emerg. Technol. Comput. Syst. Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
2015	A	`conf`	Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing. DATE Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan
2014	—	`—`	Computing with Spintronics: Circuits and architectures Rangharajan Venkatesan
2014	A	`conf`	SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing. ISLPED Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
2014	A*	`conf`	STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies. ISCA Rangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2013	A	`conf`	DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes. DATE Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
2013	A	`conf`	Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches. ISLPED Mrigank Sharad, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
2013	—	`conf`	Reading spin-torque memory with spin-torque sensors. NANOARCH Mrigank Sharad, Rangharajan Venkatesan, Xuanyao Fong, Anand Raghunathan, Kaushik Roy
2012	A	`conf`	TapeCache: a high density, energy efficient cache based on domain wall memory. ISLPED Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
2011	—	`conf`	Energy efficient many-core processor for recognition and mining using spin-based memory. NANOARCH Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan
2011	A	`conf`	MACACO: Modeling and analysis of circuits for approximate computing. ICCAD Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan
2011	A	`conf`	VESPA: Variability emulation for System-on-Chip performance analysis. DATE Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey