Ranga Vemuri - RankMe

284 papers A* 14A 44B 15C 33Misc 42Journal 36Unranked 98

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Assertion-Based Trojan Localization Using Iterative Path Sensitization. ISQED Suriya Srinivasan, Andrew Jones, Cameron Hingson, Gannon Darrach, Ranga Vemuri
2024	—	`conf`	ACT: Attributed Circuit Transformation System for Synthetic Circuit Generation. MWSCAS Juneet Kumar Meka, Ranga Vemuri
2024	—	`conf`	Combined Split Manufacturing and Logic Obfuscation Based on Emerging Technologies at High Level for Secure 3D IC Design. MWSCAS Haimanti Chakraborty, Ranga Vemuri
2024	Misc	`conf`	Enhancing Output Corruption Through GSHE Switch Based Logic Encryption. VLSID Nikhil Saxena, Ranga Vemuri
2024	—	`conf`	NoC-Armor: Leveraging Quantitative Analysis for Enhanced Security. MWSCAS Padmaja Bhamidipati, Ranga Vemuri
2024	Misc	`conf`	Pattern Based Synthetic Benchmark Generation for Hardware Security Applications. VLSID Juneet Kumar Meka, Satya AmarKant Marupureddy, Ranga Vemuri
2024	—	`conf`	QA-NoCs: Quantitative Analysis for Trojan Detection in Network-on-Chips. ISVLSI Padmaja Bhamidipati, Ranga Vemuri
2024	Misc	`conf`	ROBUST: RTL OBfuscation USing Bi-functional Polymorphic OperaTors. VLSID Haimanti Chakraborty, Ranga Vemuri
2024	—	`conf`	RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware Generation. ISQED Haimanti Chakraborty, Ranga Vemuri
2024	J	`jnl`	RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware Generation. CoRR Haimanti Chakraborty, Ranga Vemuri
2024	Misc	`conf`	Trojan Localization Using Information Flow Tracking Properties in SoC Designs. VLSID Suriya Srinivasan, Ranga Vemuri
2023	Misc	`conf`	ASPIRE: An Intermediate Representation for Abstract Security Policies. VLSID Padmaja Bhamidipati, Ranga Vemuri
2023	—	`conf`	Attributed Graph Transformation for Generating Synthetic Benchmarks for Hardware Security. ISQED Juneet Kumar Meka, Ranga Vemuri
2023	—	`conf`	Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption. MWSCAS Nikhil Saxena, Ranga Vemuri
2023	J	`jnl`	Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption. IEEE Access Nikhil Saxena, Ranga Vemuri
2023	Misc	`conf`	Mutation Analysis and Model Checking Guided Test Generation for SoC Run-Time Monitors. VLSID Suriya Srinivasan, Ranga Vemuri
2023	—	`conf`	RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks. MWSCAS Kishore Pula, Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Sundarakumar Muthukumaran, Ranga Vemuri, John Marty Emmert
2023	—	`conf`	Reverse Engineering Word-Level Models from Look-Up Table Netlists. ISQED Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri
2023	J	`jnl`	Reverse Engineering Word-Level Models from Look-Up Table Netlists. CoRR Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri
2023	—	`conf`	Reverse Engineering of RTL Controllers from Look-Up Table Netlists. ISVLSI Sundarakumar Muthukumaran, Aparajithan Nathamuni Venkatesan, Kishore Pula, Ram Venkat Narayanan, Ranga Vemuri, John Marty Emmert
2023	—	`conf`	Split Manufacturing Based Secure Hardware Design by BEOL Signal Selection In High Level Synthesis. MWSCAS Haimanti Chakraborty, Ranga Vemuri
2023	Misc	`conf`	Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information. VLSID Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri
2023	J	`jnl`	Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information. CoRR Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri
2022	—	`conf`	Analysis of the Satisfiability Attack Against Logic Encryption Using Synthetic Benchmarks. iSES Juneet Kumar Meka, Shrinidhi Venkatesh, Ranga Vemuri
2022	—	`conf`	Efficient Method for Timing-based Information Flow Verification in Hardware Designs. ACM Great Lakes Symposium on VLSI Khitam M. Alatoun, Ranga Vemuri
2022	—	`ch.`	Encoding of Finite-State Controllers for Graded Security and Power. Behavioral Synthesis for Hardware Security Richa Agrawal, Ranga Vemuri
2022	—	`conf`	FPGA Acceleration of a Stochastic Local Search Portfolio Solver for Boolean Satisfiability. MWSCAS Christopher Chuvalas, Ranga Vemuri
2022	C	`conf`	FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory. VLSI-SoC Christopher Chuvalas, Ranga Vemuri
2022	—	`conf`	ISPLock: A Hybrid Internal State Locking Method Using Polymorphic Gates. ISVLSI Nikhil Saxena, Ranga Vemuri
2022	C	`conf`	Model Checking Leveraged Error Localization for Complex RTL Designs. ICCD Suriya Srinivasan, Ranga Vemuri
2022	—	`ch.`	S*FSMs for Reduced Information Leakage: Power Side Channel Protection Through Secure Encoding. Behavioral Synthesis for Hardware Security Mike Borowczak, Ranga Vemuri
2021	—	`conf`	Educating the Next Generation of Cybersecurity Defenders at the University of Cincinnati. MWSCAS Carla Purdy, John Marty Emmert, Rashmi Jha, Ranga Vemuri
2021	C	`conf`	Efficient Methods for SoC Trust Validation Using Information Flow Verification. ICCD Khitam M. Alatoun, Shanmukha Murali Achyutha, Ranga Vemuri
2021	J	`jnl`	Logic Encryption for Resource Constrained Designs. IEEE Access David M. Luria, Ranga Vemuri
2021	—	`conf`	SRTLock: A Sensitivity Resilient Two-Tier Logic Encryption Scheme. iSES Nikhil Saxena, Ram Venkat Narayanan, Juneet Kumar Meka, Ranga Vemuri
2021	—	`conf`	Security Analysis of a System-on-Chip Using Assertion-Based Verification. MWSCAS Padmaja Bhamidipati, Shanmukha Murali Achyutha, Ranga Vemuri
2021	—	`conf`	Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip. ISVLSI Subashree Raja, Padmaja Bhamidipati, Xiaobang Liu, Ranga Vemuri
2021	—	`conf`	SoC Trust Validation Using Assertion-Based Security Monitors. ISQED Khitam Alatoun, Bharath Shankaranarayanan, Shanmukha Murali Achyutha, Ranga Vemuri
2020	—	`conf`	SLED: Sequential Logic Encryption Using Dynamic Keys. MWSCAS Yasaswy Kasarabada, Vaishali Muralidharan, Ranga Vemuri
2020	—	`conf`	Signal Selection Heuristics for Post-Silicon Validation. ISQED Suprajaa Tummala, Xiaobang Liu, Ranga Vemuri
2020	Misc	`conf`	StateLock: State Transition Based Logic Locking for Sequential Circuits. VLSID Yasaswy Kasarabada, Ranga Vemuri
2019	Misc	`conf`	A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration. VLSID Richa Agrawal, Mike Borowczak, Ranga Vemuri
2019	J	`jnl`	A State Machine Encoding Methodology Against Power Analysis Attacks. J. Electron. Test. Richa Agrawal, Ranga Vemuri, Mike Borowczak
2019	—	`conf`	Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation. ISQED Xiaobang Liu, Ranga Vemuri
2019	—	`conf`	Deep State Encryption for Sequential Logic Circuits. ISVLSI Yasaswy Kasarabada, Sudheer Ram Thulasi Raman, Ranga Vemuri
2019	—	`conf`	Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits. HOST Suyuan Chen, Ranga Vemuri
2019	J	`jnl`	Mitigating information leakage during critical communication using S*FSM. IET Comput. Digit. Tech. Mike Borowczak, Ranga Vemuri
2019	—	`conf`	Non-Invasive Reverse Engineering of Finite State Machines Using Power Analysis and Boolean Satisfiability. MWSCAS Harsh Vamja, Richa Agrawal, Ranga Vemuri
2019	J	`jnl`	Non-Invasive Reverse Engineering of Finite State Machines Using Power Analysis and Boolean Satisfiability. CoRR Harsh Vamja, Richa Agrawal, Ranga Vemuri
2019	—	`conf`	On SAT-Based Attacks On Encrypted Sequential Logic Circuits. ISQED Yasaswy Kasarabada, Suyuan Chen, Ranga Vemuri
2019	—	`conf`	Trust in IoT Devices: A Logic Encryption Perspective. IFIPIoT Yasaswy Kasarabada, David M. Luria, Ranga Vemuri
2018	C	`conf`	A secure tunable-precision architecture for image processing applications. ICCE Ankita Manjunath Nayak, Ranga Vemuri
2018	Misc	`conf`	Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation. VLSID Xiaobang Liu, Ranga Vemuri
2018	—	`conf`	Detection of Sequential Trojans in Embedded System Designs Without Scan Chains. ISVLSI Pranav Dharmadhikari, Akhilesh Raju, Ranga Vemuri
2018	—	`conf`	Fast Heuristics for Near-Optimal Signal Restoration in Post-Silicon Validation. ISVLSI Xiaobang Liu, Ranga Vemuri
2018	—	`conf`	Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection Method. ACM Great Lakes Symposium on VLSI Suyuan Chen, Ranga Vemuri
2018	—	`conf`	On state encoding against power analysis attacks for finite state controllers. HOST Richa Agrawal, Ranga Vemuri
2018	C	`conf`	On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits. VLSI-SoC Suyuan Chen, Ranga Vemuri
2018	C	`conf`	Progressive and secure performance unlocking for digital integrated circuits. ICCE Renuka Lokare, Ranga Vemuri
2018	C	`conf`	Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability Checking. ICCD Suyuan Chen, Ranga Vemuri
2017	C	`conf`	Effective Signal Restoration in Post-Silicon Validation. ICCD Xiaobang Liu, Ranga Vemuri
2016	C	`conf`	A novel simulation based approach for trace signal selection in silicon debug. ICCD Prabanjan Komari, Ranga Vemuri
2016	J	`jnl`	Fast Inversions in Small Finite Fields by Using Binary Trees. Comput. J. Haibo Yi, Shaohua Tang, Ranga Vemuri
2014	—	`conf`	Enabling Side Channel Secure FSMs in the Presence of Low Power Requirements. ISVLSI Mike Borowczak, Ranga Vemuri
2014	—	`conf`	MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs. SoCC Ramesh Nair, Ranga Vemuri
2013	—	`conf`	Design automation flow for voltage adaptive optimum granularity LITHE for sequential circuits. SoCC Venkat Krishnan Balasubramanian, Hao Xu, Ranga Vemuri
2013	—	`conf`	Secure controllers: Requirements of S*FSM. MWSCAS Mike Borowczak, Ranga Vemuri
2012	—	`conf`	A Heterogeneous Cache Distribution with Reconfigurable Interconnect. IPDPS Workshops Aishwariya Pattabiraman, Annie Avakian, Ranga Vemuri
2012	—	`conf`	Reconfigurable Multicore Architecture for Dynamic Processor Reallocation. ARC Annie Avakian, Natwar Agrawal, Ranga Vemuri
2012	—	`conf`	SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits. HOST Lakshmi Narasimhan Ramakrishnan, Manoj Chakkaravarthy, Antarpreet Singh Manchanda, Mike Borowczak, Ranga Vemuri
2011	J	`jnl`	Aggressive Runtime Leakage Control Through Adaptive Light-Weight V IEEE Trans. Very Large Scale Integr. Syst. Hao Xu, Wen-Ben Jone, Ranga Vemuri
2011	—	`conf`	Configurable workload generators for multicore architectures. SoCC Amayika Panda, Annie Avakian, Ranga Vemuri
2011	J	`jnl`	Dynamic Characteristics of Power Gating During Mode Transition. IEEE Trans. Very Large Scale Integr. Syst. Hao Xu, Ranga Vemuri, Wen-Ben Jone
2010	—	`conf`	A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems. SoCC Jon Nafziger, Annie Avakian, Ranga Vemuri
2010	—	`conf`	A reconfigurable architecture for multicore systems. IPDPS Workshops Annie Avakian, Jon Nafziger, Amayika Panda, Ranga Vemuri
2010	A	`conf`	Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. ICCAD Hao Xu, Ranga Vemuri, Wen-Ben Jone
2010	Misc	`conf`	Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. VLSI Design Hao Xu, Wen-Ben Jone, Ranga Vemuri
2010	A	`conf`	Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. ICCAD Hao Xu, Wen-Ben Jone, Ranga Vemuri
2010	J	`jnl`	Tuning J. Low Power Electron. Hao Xu, Wen-Ben Jone, Ranga Vemuri
2009	A	`conf`	A graph grammar based approach to automated multi-objective analog circuit design. DATE Angan Das, Ranga Vemuri
2009	—	`conf`	A methodology for application-specific NoC architecture generation in a dynamic task structure environment. ACM Great Lakes Symposium on VLSI Balasubramanian Sethuraman, Ranga Vemuri
2009	C	`conf`	Accurate estimation of vector dependent leakage power in the presence of process variations. ICCD Romana Fernandes, Ranga Vemuri
2009	Misc	`conf`	Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. VLSI Design Almitra Pradhan, Ranga Vemuri
2009	Misc	`conf`	Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design. VLSI Design Angan Das, Ranga Vemuri
2009	A	`conf`	Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. DATE Hao Xu, Ranga Vemuri, Wen-Ben Jone
2009	A	`conf`	Temporal and spatial idleness exploitation for optimal-grained leakage control. ICCAD Hao Xu, Ranga Vemuri, Wen-Ben Jone
2009	Misc	`conf`	Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. VLSI Design Shubhankar Basu, Balaji Kommineni, Ranga Vemuri
2008	—	`conf`	A Self-learning Optimization Technique for Topology Design of Computer Networks. EvoWorkshops Angan Das, Ranga Vemuri
2008	—	`conf`	A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection. ACM Great Lakes Symposium on VLSI Almitra Pradhan, Ranga Vemuri
2008	C	`conf`	ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework. ISCAS Angan Das, Ranga Vemuri
2008	A	`conf`	Accurate energy breakeven time estimation for run-time power gating. ICCAD Hao Xu, Wen-Ben Jone, Ranga Vemuri
2008	A	`conf`	Dynamic virtual ground voltage estimation for power gating. ISLPED Hao Xu, Ranga Vemuri, Wen-Ben Jone
2008	A	`conf`	Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches. DATE Almitra Pradhan, Ranga Vemuri
2008	Misc	`conf`	Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples. VLSI Design Shubhankar Basu, Balaji Kommineni, Ranga Vemuri
2008	Misc	`conf`	On the Use of Hash Tables for Efficient Analog Circuit Synthesis. VLSI Design Almitra Pradhan, Ranga Vemuri
2008	Misc	`conf`	Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design. VLSI Design Srividhya Rammohan, Vijay Sundaresan, Ranga Vemuri
2008	C	`conf`	Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. ICCD Hao Xu, Ranga Vemuri, Wen-Ben Jone
2008	A*	`conf`	Topology synthesis of analog circuits based on adaptively generated building blocks. DAC Angan Das, Ranga Vemuri
2008	—	`conf`	Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. ISQED Shubhankar Basu, Balaji Kommineni, Ranga Vemuri
2007	Misc	`conf`	A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. VLSI Design Balasubramanian Sethuraman, Ranga Vemuri
2007	C	`conf`	A spline based regression technique on interval valued noisy data. ICMLA Balaji Kommineni, Shubhankar Basu, Ranga Vemuri
2007	—	`conf`	Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis. VLSI-SoC (Selected Papers) Almitra Pradhan, Ranga Vemuri
2007	—	`conf`	An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms. ISVLSI Angan Das, Ranga Vemuri
2007	J	`jnl`	An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms CoRR Jawad Khan, Ranga Vemuri
2007	Misc	`conf`	Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. VLSI Design Huiying Yang, Ranga Vemuri
2007	C	`conf`	GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis. ISCAS Angan Das, Ranga Vemuri
2007	J	`jnl`	Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis CoRR Raoul F. Badaoui, Ranga Vemuri
2007	A	`conf`	Multicasting based topology generation and core mapping for a power efficient networks-on-chip. ISLPED Balasubramanian Sethuraman, Ranga Vemuri
2007	C	`conf`	Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. VLSI-SoC Vijay Sundaresan, Srividhya Rammohan, Ranga Vemuri
2007	C	`conf`	Power variations of multi-port routers in an application-specific NoC design : A case study. ICCD Balasubramanian Sethuraman, Ranga Vemuri
2007	—	`conf`	Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. ISQED Shubhankar Basu, Priyanka Thakore, Ranga Vemuri
2007	—	`conf`	Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. ISVLSI Shubhankar Basu, Ranga Vemuri
2007	C	`conf`	Regression based circuit matrix models for accurate performance estimation of analog circuits. VLSI-SoC Almitra Pradhan, Ranga Vemuri
2006	—	`conf`	A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. ISVLSI Vijay Sundaresan, Ranga Vemuri
2006	Misc	`conf`	CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture. VLSI Design Xin Jia, Ranga Vemuri
2006	Misc	`conf`	Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. VLSI Design Mengmeng Ding, Ranga Vemuri
2006	A	`conf`	Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. DATE Huiying Yang, Ranga Vemuri
2006	J	`jnl`	Energy management for battery-powered reconfigurable computing platforms. IEEE Trans. Very Large Scale Integr. Syst. Jawad Khan, Ranga Vemuri
2006	C	`conf`	Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. ISCAS Mukesh Ranjan, Ranga Vemuri
2006	J	`jnl`	Hierarchical constraint transformation based on genetic optimization for analog system synthesis. Integr. Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri
2006	B	`conf`	Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip. FPL Balasubramanian Sethuraman, Ranga Vemuri
2006	Misc	`conf`	Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics. VLSI Design Amitava Bhaduri, Ranga Vemuri
2006	A	`conf`	Studying a GALS FPGA architecture using a parameterized automatic design flow. ICCAD Xin Jia, Ranga Vemuri
2006	Misc	`conf`	Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. VLSI Design Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri
2006	—	`conf`	Transformation synthesis for data intensive applications to FPGAs. ACM Great Lakes Symposium on VLSI Renqiu Huang, Ranga Vemuri
2006	A	`conf`	optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs. DATE Balasubramanian Sethuraman, Ranga Vemuri
2005	B	`conf`	A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation. FPL Xin Jia, Ranga Vemuri
2005	A	`conf`	A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling. DATE Mengmeng Ding, Ranga Vemuri
2005	A*	`conf`	A combined feasibility and performance macromodel for analog circuits. DAC Mengmeng Ding, Ranga Vemuri
2005	—	`conf`	Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. ACM Great Lakes Symposium on VLSI Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri
2005	Misc	`conf`	An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification. VLSI Design Mengmeng Ding, Ranga Vemuri
2005	A	`conf`	An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms. DATE Jawad Khan, Ranga Vemuri
2005	—	`conf`	An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. ASP-DAC Mengmeng Ding, Glenn Wolfe, Ranga Vemuri
2005	—	`conf`	Analog VLSI circuit-level synthesis using multi-placement structures. ISCAS (6) Raoul F. Badaoui, Ranga Vemuri
2005	A	`conf`	Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units. IPDPS Jawad Khan, Ranga Vemuri
2005	—	`conf`	Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. ASP-DAC Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen
2005	B	`conf`	Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes. FPL Jawad Khan, Ranga Vemuri
2005	—	`conf`	Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. ISVLSI Huiying Yang, Anuradha Agarwal, Ranga Vemuri
2005	J	`jnl`	Hardware assisted two dimensional ultra fast online placement. Int. J. Embed. Syst. Manish Handa, Ranga Vemuri
2005	A	`conf`	Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. ICCAD Anuradha Agarwal, Ranga Vemuri
2005	A	`conf`	Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric. DATE Amitava Bhaduri, Ranga Vemuri
2005	C	`conf`	Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. ICCD Anuradha Agarwal, Ranga Vemuri
2005	—	`conf`	LiPaR: A light-weight parallel router for FPGA-based networks-on-chip. ACM Great Lakes Symposium on VLSI Balasubramanian Sethuraman, Prasun Bhattacharya, Jawad Khan, Ranga Vemuri
2005	—	`conf`	Moment-driven coupling-aware routing methodology. ACM Great Lakes Symposium on VLSI Amitava Bhaduri, Ranga Vemuri
2005	A	`conf`	Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. DATE Raoul F. Badaoui, Ranga Vemuri
2005	Misc	`conf`	On Physical-Aware Synthesis of Vertically Integrated 3D Systems. VLSI Design Madhubanti Mukherjee, Ranga Vemuri
2005	Misc	`conf`	On-Line Synthesis for Partially Reconfigurable FPGAs. VLSI Design Renqiu Huang, Ranga Vemuri
2005	B	`conf`	PAHLS: Towards Run-Time Synthesis for FPGAs. FPL Renqiu Huang, Ranga Vemuri
2005	—	`conf`	Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs. ISVLSI Renqiu Huang, Ranga Vemuri
2005	Misc	`conf`	The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture. FCCM Xin Jia, Ranga Vemuri
2005	—	`conf`	Using GALS architecture to reduce the impact of long wire delay on FPGA performance. ASP-DAC Xin Jia, Ranga Vemuri
2004	—	`conf`	A Design Methodology for Self-Timed Event Logic Pipelines. ESA/VLSI Xin Jia, Ranga Vemuri
2004	B	`conf`	A Dynamically Reconfigurable Asynchronous FPGA Architecture. FPL Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri
2004	A	`conf`	A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement. DATE Manish Handa, Ranga Vemuri
2004	—	`conf`	A Portable Face Recognition System Using Reconfigurable Hardware. ERSA Jawad Khan, Jayanthi Rajagopalan, Renqiu Huang, Ranga Vemuri
2004	—	`conf`	A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms. ERSA Jawad Khan, Balasubramanian Sethuraman, Ranga Vemuri
2004	—	`conf`	A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. ACM Great Lakes Symposium on VLSI Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri
2004	J	`jnl`	A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. ACM Trans. Design Autom. Electr. Syst. Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
2004	A	`conf`	Accurate Estimation of Parasitic Capacitances in Analog Circuits. DATE Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
2004	A	`conf`	Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. ICCAD Ranga Vemuri, Glenn Wolfe
2004	B	`conf`	An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms. FPL Jawad Khan, Ranga Vemuri
2004	B	`conf`	An Integrated Online Scheduling and Placement Methodology. FPL Manish Handa, Ranga Vemuri
2004	A*	`conf`	An efficient algorithm for finding empty space for online FPGA placement. DAC Manish Handa, Ranga Vemuri
2004	A	`conf`	Analysis and evaluation of a hybrid interconnect structure for FPGAs. ICCAD Renqiu Huang, Ranga Vemuri
2004	B	`conf`	Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs. FPL Renqiu Huang, Manish Handa, Ranga Vemuri
2004	—	`conf`	Area Fragmentation in Reconfigurable Operating Systems. ERSA Manish Handa, Ranga Vemuri
2004	—	`conf`	Battery-efficient task execution on portable reconfigurable computing. SoCC Balasubramanian Sethuraman, Jawad Khan, Ranga Vemuri
2004	A*	`conf`	Fast and accurate parasitic capacitance models for layout-aware. DAC Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
2004	A	`conf`	Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. DATE Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen
2004	A	`conf`	Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs. IPDPS Renqiu Huang, Ranga Vemuri
2004	A	`conf`	Hardware Assisted Two Dimensional Ultra Fast Placement. IPDPS Manish Handa, Ranga Vemuri
2004	C	`conf`	Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems. ICCD Madhubanti Mukherjee, Ranga Vemuri
2003	Misc	`conf`	A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs. VLSI Design Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri
2003	C	`conf`	A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. ICCD Madhubanti Mukherjee, Ranga Vemuri
2003	C	`conf`	Adaptive Sampling and Modeling of Analog Circuit Performance Parameters. VLSI-SOC Glenn Wolfe, Mengmeng Ding, Ranga Vemuri
2003	J	`jnl`	Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alex Doboli, Ranga Vemuri
2003	J	`jnl`	Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alex Doboli, Ranga Vemuri
2003	J	`jnl`	Extraction and use of neural network models in automated synthesis of operational amplifiers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Glenn Wolfe, Ranga Vemuri
2003	C	`conf`	MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators. VLSI-SOC Hemanth Sampath, Ranga Vemuri
2002	A	`conf`	A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems. DATE Alex Doboli, Ranga Vemuri
2002	J	`jnl`	An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. ACM Trans. Design Autom. Electr. Syst. Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy
2002	—	`conf`	Framework for Synthesis of Virtual Pipelines. ASP-DAC/VLSI Design Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri
2002	J	`jnl`	Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Trans. Very Large Scale Integr. Syst. Karam S. Chatha, Ranga Vemuri
2002	B	`conf`	iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications. FPL Jawad Khan, Manish Handa, Ranga Vemuri
2001	A	`conf`	A regularity-based hierarchical symbolic analysis method for large-scale analog networks. DATE Alex Doboli, Ranga Vemuri
2001	—	`conf`	Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems. ARVLSI Sree Ganesan, Ranga Vemuri
2001	Misc	`conf`	Application Specific Macro Based Synthesis. VLSI Design Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri
2001	A*	`conf`	Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems. DAC Sree Ganesan, Ranga Vemuri
2001	A	`conf`	Continous Wavelet Transform on Reconfigurable Meshes. IPDPS Yi Pan, Jie Li, Ranga Vemuri
2001	J	`jnl`	Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures. IEEE Trans. Very Large Scale Integr. Syst. V. Srinivasan, Sriram Govindarajan, Ranga Vemuri
2001	A	`conf`	Global memory mapping for FPGA-based reconfigurable systems. IPDPS Iyad Ouaiss, Ranga Vemuri
2001	J	`jnl`	Guest editorial reconfigurable and adaptive VLSI systems. IEEE Trans. Very Large Scale Integr. Syst. Ranga Vemuri, Rajesh K. Gupta
2001	A	`conf`	Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. DATE Iyad Ouaiss, Ranga Vemuri
2001	—	`conf`	Hierarchical performance optimization for synthesis of linear analog systems. ISCAS (5) Alex Doboli, Ranga Vemuri
2001	A*	`conf`	Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints. DAC Alex Doboli, Ranga Vemuri
2001	Misc	`conf`	Library Binding for High-Level Synthesis of Analog Systems. VLSI Design Sree Ganesan, Ranga Vemuri
2001	—	`conf`	MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. CODES Karam S. Chatha, Ranga Vemuri
2001	B	`conf`	Memory Synthesis for FPGA-Based Reconfigurable Computers. FPL Amit Kasat, Iyad Ouaiss, Ranga Vemuri
2001	A	`conf`	On the verification of synthesized designs using automatically generated transformational witnesses. DATE Elena Teica, Rajesh Radhakrishnan, Ranga Vemuri
2001	J	`jnl`	Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis. Formal Methods Syst. Des. Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri
2001	—	`conf`	Verification of Basic Block Schedules Using RTL Transformations. CHARME Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri
2000	Misc	`conf`	A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. VLSI Design Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri
2000	C	`conf`	A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems. ISCAS Alex Doboli, Nagu R. Dhanwada, Ranga Vemuri
2000	A	`conf`	An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement. DATE Satish Ganesan, Ranga Vemuri
2000	J	`jnl`	An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling. Des. Autom. Embed. Syst. Karam S. Chatha, Ranga Vemuri
2000	—	`conf`	An approach to high-level synthesis system validation using formally verified transformations. HLDVT Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri
2000	J	`jnl`	Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs. Formal Methods Syst. Des. Nazanin Mansouri, Ranga Vemuri
2000	—	`conf`	Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints. IPDPS Workshops Preetham Lakshmikanthan, Sriram Govindarajan, Vinoo Srinivasan, Ranga Vemuri
2000	J	`jnl`	Configurable Computing: Technology and Applications - Guest Editors' Introduction. Computer Ranga Vemuri, Randolph E. Harr
2000	J	`jnl`	Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems. J. VLSI Signal Process. Meenakshi Kaul, Ranga Vemuri
2000	A	`conf`	Efficient Resource Arbitration in Reconfigurable Computing Environments. DATE Iyad Ouaiss, Ranga Vemuri
2000	Misc	`conf`	Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. VLSI Design Abhijit Ghosh, Ranga Vemuri
2000	A	`conf`	Improving the Schedule Quality of Static-List Time-Constrained Scheduling. DATE Sriram Govindarajan, Ranga Vemuri
2000	C	`conf`	Scheduling for low power under resource and latency constraints. ISCAS Srinivas Katkoori, Ranga Vemuri
2000	A	`conf`	Technology Mapping and Retargeting for Field-Programmable Analog Arrays. DATE Sree Ganesan, Ranga Vemuri
2000	B	`conf`	Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS. FPL Sriram Govindarajan, Ranga Vemuri
2000	—	`conf`	Towards a Specification Notation for High-Level Synthesis of Mixed-Signal and Analog Systems. BMAS Alex Doboli, Ranga Vemuri
1999	—	`conf`	A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications. VLSI Alex Doboli, Ranga Vemuri
1999	—	`conf`	A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements. VLSI Adrián Núñez-Aldana, Ranga Vemuri
1999	C	`conf`	A Methodology for Rapid Prototyping of Analog Systems. ICCD Sree Ganesan, Ranga Vemuri
1999	A	`conf`	A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems. DATE Alex Doboli, Ranga Vemuri
1999	—	`conf`	A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis. ISCAS (6) Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
1999	A	`conf`	Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. DATE Nazanin Mansouri, Ranga Vemuri
1999	—	`conf`	Accurate Resource Estimation Algorithms for Behavioral Synthesis. Great Lakes Symposium on VLSI Srinivas Katkoori, Ranga Vemuri
1999	A	`conf`	An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis. DATE Adrián Núñez-Aldana, Ranga Vemuri
1999	A*	`conf`	An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. DAC Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss
1999	C	`conf`	An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. IEEE International Workshop on Rapid System Prototyping Karam S. Chatha, Ranga Vemuri
1999	—	`conf`	Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. ASP-DAC Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
1999	A*	`conf`	Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. DAC Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri
1999	Misc	`conf`	Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis. VLSI Design Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
1999	Misc	`conf`	FAAR: A Router for Field-Programmable Analog Arrays. VLSI Design Sree Ganesan, Ranga Vemuri
1999	C	`conf`	Formal Verification of Synthesized Analog Designs. ICCD Abhijit Ghosh, Ranga Vemuri
1999	B	`conf`	Hardware-Software Codesign for Dynamically Reconfigurable Architectures. FPL Karam S. Chatha, Ranga Vemuri
1999	A	`conf`	Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. DATE Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
1999	—	`conf`	Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops. Great Lakes Symposium on VLSI Abhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri
1999	—	`conf`	Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures. IPPS/SPDP Workshops Meenakshi Kaul, Ranga Vemuri
1999	—	`conf`	Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures. IPPS/SPDP Workshops Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri, Jeffrey Walrath
1999	Misc	`conf`	Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures. FCCM Vinoo Srinivasan, Ranga Vemuri
1999	A	`conf`	Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. DATE Meenakshi Kaul, Ranga Vemuri
1999	A	`conf`	Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures. FPGA Vinoo Srinivasan, Ranga Vemuri
1998	B	`conf`	A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. FMCAD Nazanin Mansouri, Ranga Vemuri
1998	—	`conf`	A Performance Modeling and Analysis Environment for Reconfigurable Computers. IPPS/SPDP Workshops Jeffrey Walrath, Ranga Vemuri
1998	Misc	`conf`	A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining. VLSI Design Vinoo Srinivasan, Ranga Vemuri
1998	—	`conf`	A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. ISSS Karam S. Chatha, Ranga Vemuri
1998	Misc	`conf`	An Effective Design System for Dynamically Reconfigurable Architectures. FCCM Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri
1998	—	`conf`	An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. IPPS/SPDP Workshops Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri
1998	J	`jnl`	Architectural Power Estimation Based on Behavior Level Profiling. VLSI Design Srinivas Katkoori, Ranga Vemuri
1998	C	`conf`	Automatic data path abstraction for verification of large scale designs. ICCD Viresh Paruthi, Nazanin Mansouri, Ranga Vemuri
1998	Misc	`conf`	Constraint Allocation in Analog System Synthesis. VLSI Design Nagu R. Dhanwada, Ranga Vemuri
1998	A	`conf`	Hardware Software Partitioning with Integrated Hardware Design Space Exploration. DATE Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri
1998	—	`conf`	On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System. TPHOLs Naren Narasimhan, Ranga Vemuri
1998	A	`conf`	Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures. DATE Meenakshi Kaul, Ranga Vemuri
1998	C	`conf`	Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. International Workshop on Rapid System Prototyping Karam S. Chatha, Ranga Vemuri
1998	—	`conf`	RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. CODES Karam S. Chatha, Ranga Vemuri
1998	C	`conf`	Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis. ICCD Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri
1997	—	`conf`	A constructive method for data path area estimation during high-level VLSI synthesis. ASP-DAC Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri
1997	—	`conf`	Cone-based clustering heuristic for list-scheduling algorithms. ED&TC Sriram Govindarajan, Ranga Vemuri
1997	C	`conf`	Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms. ICCD Sriram Govindarajan, Ranga Vemuri
1997	—	`conf`	Performance verification using partial evaluation and interval analysis. ED&TC Jeffrey Walrath, Ranga Vemuri, W. Bradley
1997	Misc	`conf`	Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs. VLSI Design Madhavi Vootukuru, Ranga Vemuri, Nand Kumar
1997	A*	`conf`	Symbolic Evaluation of Performance Models for Tradeoff Visualization. DAC Jeffrey Walrath, Ranga Vemuri
1996	Misc	`conf`	A Hierarchical Register Optimization Algorithm for Behavioral Synthesis. VLSI Design Srinivas Katkoori, Ranga Vemuri, Jay Roy
1996	—	`conf`	Hierarchical behavioral partitioning for multicomponent synthesis. EURO-DAC Vinoo Srinivasan, Nand Kumar, Ranga Vemuri
1996	J	`jnl`	Performance Modeling Using PDL. Computer Ranga Vemuri, Ram Manday, Vijay Meduri
1996	—	`conf`	Rapid Prototyping of Reconfigurable Coprocessors. ASAP Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri
1996	A	`conf`	Simulation based architectural power estimation for PLA-based controllers. ISLPED Srinivas Katkoori, Ranga Vemuri
1996	B	`conf`	Specification of Control Flow Properties for Verification of Synthesized VHDL Designs. FMCAD Naren Narasimhan, Ranga Vemuri
1996	Misc	`conf`	Synchronous Controller Models for Synthesis from Communicating VHDL Processes. VLSI Design Naren Narasimhan, Ranga Vemuri, Jay Roy
1995	J	`jnl`	Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. IEEE Trans. Very Large Scale Integr. Syst. Ranga Vemuri, R. Kalyanaraman
1995	C	`conf`	High level profiling based low power synthesis technique. ICCD Srinivas Katkoori, Nand Kumar, Ranga Vemuri
1995	J	`jnl`	Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems. IEEE Des. Test Comput. Nand Kumar, Srinivas Katkoori, Leo Rader, Ranga Vemuri
1995	Misc	`conf`	Transformations for functional verification of synthesized designs. VLSI Design William L. Bradley, Ranga Vemuri
1993	J	`jnl`	An Integrated Multicomponent Synthesis for MCMs. Computer Ranga Vemuri, Nand Kumar, Raghu Vutukuru, Prasad Subba Rao, Praveen Sinha, Ning Ren, Paddy Mamtora, Ram Mandayam, Ram Vemuri, Jayanta Roy
1993	A*	`conf`	Experiences in Functional Validation of a High Level Synthesis System. DAC Ranga Vemuri, Paddy Mamtora, Praveen Sinha, Nand Kumar, Jayanta Roy, Raghu Vutukuru
1993	A*	`conf`	Performance Specification Using Attributed Grammars. DAC Ram Mandayam, Ranga Vemuri
1993	—	`conf`	Performance Specification and Measurement. CHDL Ram Mandayam, Ranga Vemuri
1992	J	`jnl`	DSS: A Distributed High-Level Synthesis System. IEEE Des. Test Comput. Jayanta Roy, Nand Kumar, Rajiv Dutta, Ranga Vemuri
1992	A*	`conf`	Distributed Design-Space Exploration for High-Level Synthesis Systems. DAC Rajiv Dutta, Jayanta Roy, Ranga Vemuri
1992	—	`conf`	Finite state machine verification on MIMD machines. EURO-DAC Nand Kumar, Ranga Vemuri
1991	—	`conf`	Genetic synthesis: performance-driven logic synthesis using genetic evolution. Great Lakes Symposium on VLSI Ram Vemuri, Ranga Vemuri
1991	A*	`conf`	Temporal Precondition Verification of Design Transformations. CAV Ranga Vemuri, Anuradha Sridhar
1990	—	`conf`	On the notion of the normal form register-level structures and its applications in design-space exploration. EURO-DAC Ranga Vemuri
1986	A*	`conf`	Data flow graph partitioning to reduce communication cost. MICRO Cris Koutsougeras, Christos A. Papachristou, Ranga Vemuri
1978	B	`conf`	Continuing education in microprocessors: Use of software simulators. COMPSAC Ranga Vemuri, J. V. Cornacchio