Ran Ginosar - RankMe

156 papers A* 5A 5B 6C 7Misc 1Journal 82Unranked 49

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Theoretical complexity analysis of many-cores on a single chip. CoRR Ran Ginosar
2022	J	`jnl`	GIRAF: General Purpose In-Storage Resistive Associative Framework. IEEE Trans. Parallel Distributed Syst. Leonid Yavits, Roman Kaplan, Ran Ginosar
2021	J	`jnl`	A survey of algorithmic methods in IC reverse engineering. IACR Cryptol. ePrint Arch. Leonid Azriel, Julian Speith, Nils Albartus, Ran Ginosar, Avi Mendelson, Christof Paar
2021	J	`jnl`	A survey of algorithmic methods in IC reverse engineering. J. Cryptogr. Eng. Leonid Azriel, Julian Speith, Nils Albartus, Ran Ginosar, Avi Mendelson, Christof Paar
2020	Misc	`conf`	BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. SYSTOR Roman Kaplan, Leonid Yavits, Ran Ginosar
2020	C	`conf`	WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. ICCD Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu
2020	J	`jnl`	WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. CoRR Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, Onur Mutlu
2019	J	`jnl`	AIDA: Associative DNN Inference Accelerator. CoRR Leonid Yavits, Roman Kaplan, Ran Ginosar
2019	J	`jnl`	Adaptive programming in multi-level cell ReRAM. Microelectron. J. Misbah Ramadan, Nicolás Wainstein, Ran Ginosar, Shahar Kvatinsky
2019	J	`jnl`	BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. CoRR Roman Kaplan, Leonid Yavits, Ran Ginosar
2019	B	`conf`	POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. PACT Roman Kaplan, Leonid Yavits, Ran Ginosar
2019	B	`conf`	POSTER: GIRAF: General Purpose In-Storage Resistive Associative Framework. PACT Leonid Yavits, Roman Kaplan, Ran Ginosar
2019	J	`jnl`	RASSA: Resistive Prealignment Accelerator for Approximate DNA Long Read Mapping. IEEE Micro Roman Kaplan, Leonid Yavits, Ran Ginosar
2019	—	`conf`	SoK: An Overview of Algorithmic Methods in IC Reverse Engineering. ASHES@CCS Leonid Azriel, Ran Ginosar, Avi Mendelson
2018	J	`jnl`	Accelerator for Sparse Machine Learning. IEEE Comput. Archit. Lett. Leonid Yavits, Ran Ginosar
2018	J	`jnl`	Enabling Full Associativity with Memristive Address Decoder. IEEE Micro Leonid Yavits, Roman Kaplan, Ran Ginosar
2018	J	`jnl`	PRINS: Resistive CAM Processing in Storage. CoRR Leonid Yavits, Roman Kaplan, Ran Ginosar
2018	J	`jnl`	RASSA: Resistive Accelerator for Approximate Long Read DNA Mapping. CoRR Roman Kaplan, Leonid Yavits, Ran Ginosar
2017	J	`jnl`	A 1.4×FO4 self-clocked asynchronous serial link in 0.18 µm for intrachip communication. Integr. Y. Zhang, Rostislav (Reuven) Dobkin, Aharon Unikovski, Danniel Nahmanny, Goel Samuel, Michael Moyal, Ran Ginosar
2017	J	`jnl`	A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. CoRR Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser
2017	J	`jnl`	A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. IEEE Micro Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser
2017	J	`jnl`	Cache Hierarchy Optimization. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2017	J	`jnl`	From Processing-in-Memory to Processing-in-Storage. Supercomput. Front. Innov. Roman Kaplan, Leonid Yavits, Ran Ginosar
2017	J	`jnl`	MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures. CoRR Leonid Yavits, Amir Morad, Uri C. Weiser, Ran Ginosar
2017	J	`jnl`	Resistive Address Decoder. IEEE Comput. Archit. Lett. Leonid Yavits, Uri C. Weiser, Ran Ginosar
2017	—	`conf`	Revealing On-chip Proprietary Security Functions with Scan Side Channel Based Reverse Engineering. ACM Great Lakes Symposium on VLSI Leonid Azriel, Ran Ginosar, Avi Mendelson
2017	J	`jnl`	Sparse Matrix Multiplication On An Associative Processor. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2017	J	`jnl`	Sparse Matrix Multiplication on CAM Based Accelerator. CoRR Leonid Yavits, Ran Ginosar
2017	J	`jnl`	The Effect of Temperature on Amdahl Law in 3D Multicore Era. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2017	J	`jnl`	Using Scan Side Channel to Detect IP Theft. IEEE Trans. Very Large Scale Integr. Syst. Leonid Azriel, Ran Ginosar, Shay Gueron, Avi Mendelson
2016	J	`jnl`	Convex Optimization of Real Time SoC. CoRR Leonid Yavits, Amir Morad, Ran Ginosar, Uri C. Weiser
2016	—	`conf`	Deduplication in resistive content addressable memory based solid state drive. PATMOS Roman Kaplan, Leonid Yavits, Amir Morad, Ran Ginosar
2016	J	`jnl`	Effect of Data Sharing on Private Cache Design in Chip Multiprocessors. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2016	J	`jnl`	H-EARtH: Heterogeneous Multicore Platform Energy Management. Computer Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ran Ginosar, Eliezer Weissmann, Yoni Aizik
2016	J	`jnl`	Resistive GP-SIMD Processing-In-Memory. ACM Trans. Archit. Code Optim. Amir Morad, Leonid Yavits, Shahar Kvatinsky, Ran Ginosar
2016	J	`jnl`	The Effect of Temperature on Amdahl Law in 3D Multicore Era. IEEE Trans. Computers Leonid Yavits, Amir Morad, Ran Ginosar
2016	—	`conf`	Using Scan Side Channel for Detecting IP Theft. HASP@ISCA Leonid Azriel, Ran Ginosar, Shay Gueron, Avi Mendelson
2015	J	`jnl`	A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance. IEEE Trans. Very Large Scale Integr. Syst. Salomon Beer, Ran Ginosar
2015	—	`conf`	Asynchronous sub-threshold ultra-low power processor. PATMOS Ron Diamant, Ran Ginosar, Christos P. Sotiriou
2015	J	`jnl`	Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator. IEEE Trans. Computers Leonid Yavits, Amir Morad, Ran Ginosar
2015	J	`jnl`	Eleven Ways to Boost Your Synchronizer. IEEE Trans. Very Large Scale Integr. Syst. Salomon Beer, Ran Ginosar
2015	J	`jnl`	Power and thermal constraints of modern system-on-a-chip computer. Microelectron. J. Efraim Rotem, Ran Ginosar, Avi Mendelson, Uri C. Weiser
2015	J	`jnl`	Resistive Associative Processor. IEEE Comput. Archit. Lett. Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar
2015	J	`jnl`	SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Marco Cannizzaro, Salomon Beer, Jordi Cortadella, Ran Ginosar, Luciano Lavagno
2015	J	`jnl`	Sparse Matrix Multiplication On An Associative Processor. IEEE Trans. Parallel Distributed Syst. Leonid Yavits, Amir Morad, Ran Ginosar
2015	J	`jnl`	Variability in Multistage Synchronizers. IEEE Trans. Very Large Scale Integr. Syst. Salomon Beer, Jerome Cox, Ran Ginosar, Tom Chaney, David M. Zar
2014	J	`jnl`	Cache Hierarchy Optimization. IEEE Comput. Archit. Lett. Leonid Yavits, Amir Morad, Ran Ginosar
2014	J	`jnl`	Compiler-Directed Power Management for Superscalars. ACM Trans. Archit. Code Optim. Jawad Haj-Yihia, Yosi Ben-Asher, Efraim Rotem, Ahmad Yasin, Ran Ginosar
2014	—	`conf`	Convex optimization of resource allocation in asymmetric and heterogeneous SoC. PATMOS Amir Morad, Leonid Yavits, Ran Ginosar
2014	—	`conf`	Efficient Dense and Sparse Matrix Multiplication on GP-SIMD. PATMOS Amir Morad, Leonid Yavits, Ran Ginosar
2014	J	`jnl`	Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management. IEEE Comput. Archit. Lett. Efraim Rotem, Ran Ginosar, Uri C. Weiser, Avi Mendelson
2014	—	`conf`	Energy management of highly dynamic server workloads in an heterogeneous data center. PATMOS Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ahmad Yasin, Ran Ginosar
2014	J	`jnl`	GP-SIMD Processing-in-Memory. ACM Trans. Archit. Code Optim. Amir Morad, Leonid Yavits, Ran Ginosar
2014	J	`jnl`	Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC. IEEE Comput. Archit. Lett. Amir Morad, Tomer Y. Morad, Leonid Yavits, Ran Ginosar, Uri C. Weiser
2014	J	`jnl`	Guest Editors' Introduction - Special Issue on Network-on-Chip. IEEE Trans. Computers Ran Ginosar, Karam S. Chatha
2014	—	`conf`	Hardware Scheduler Performance on the Plural Many-Core Architecture. MES@ISCA Itai Avron, Ran Ginosar
2014	—	`conf`	Metastability in Better-Than-Worst-Case Designs. ASYNC Salomon Beer, Marco Cannizzaro, Jordi Cortadella, Ran Ginosar, Luciano Lavagno
2014	J	`jnl`	StarSync: An extendable standard-cell mesochronous synchronizer. Integr. Dmitry Verbitsky, Rostislav (Reuven) Dobkin, Ran Ginosar, Salomon Beer
2014	J	`jnl`	The effect of communication and synchronization on Amdahl's law in multicore systems. Parallel Comput. Leonid Yavits, Amir Morad, Ran Ginosar
2013	J	`jnl`	3D Cache Hierarchy Optimization. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2013	—	`conf`	3D cache hierarchy optimization. 3DIC Leonid Yavits, Amir Morad, Ran Ginosar
2013	—	`conf`	MTBF Estimation in Coherent Clock Domains. ASYNC Salomon Beer, Ran Ginosar, Rostislav (Reuven) Dobkin, Yoav Weizman
2013	A	`conf`	Metastability challenges for 65nm and beyond: simulation and measurements. DATE Salomon Beer, Ran Ginosar, Jerome Cox, Tom Chaney, David M. Zar
2013	—	`conf`	PBD: packet buffer DVFs. ACM Great Lakes Symposium on VLSI Eyal-Itzhak Nave, Ran Ginosar
2013	J	`jnl`	The Effect of Communication and Synchronization on Amdahl Law in Multicore Systems. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2013	J	`jnl`	Thermal analysis of 3D associative processor. CoRR Leonid Yavits, Amir Morad, Ran Ginosar
2013	J	`jnl`	Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks. Integr. Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
2012	—	`conf`	An Extended Metastability Simulation Method for Synchronizer Characterization. PATMOS Salomon Beer, Ran Ginosar
2012	C	`conf`	Energy metrics for power efficient crosslink and mesh topologies. ISCAS Inna Vaisband, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2012	—	`conf`	Performance of a Hardware Scheduler for Many-core Architecture. HPCC-ICESS Itai Avron, Ran Ginosar
2012	—	`conf`	TCP Window Based DVFS for Low Power Network Controller SoC. PATMOS Eyal-Itzhak Nave, Ran Ginosar
2011	C	`conf`	An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm. ISCAS Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny
2011	J	`jnl`	Metastability and Synchronizers: A Tutorial. IEEE Des. Test Comput. Ran Ginosar
2011	—	`ed.`	NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011 NOCS Radu Marculescu, Michael Kishinevsky, Ran Ginosar, Karam S. Chatha
2011	J	`jnl`	Scalable network-on-chip architecture for configurable neural networks. Microprocess. Microsystems Dmitri Vainbrand, Ran Ginosar
2010	J	`jnl`	Asynchronous Current Mode Serial Communication. IEEE Trans. Very Large Scale Integr. Syst. Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar
2010	J	`jnl`	Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. Very Large Scale Integr. Syst. Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2010	—	`conf`	Network-on-Chip Architectures for Neural Networks. NOCS Dmitri Vainbrand, Ran Ginosar
2010	C	`conf`	Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip. VLSI-SoC Amit Berman, Ran Ginosar, Idit Keidar
2010	—	`conf`	The Devolution of Synchronizers. ASYNC Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny
2010	—	`conf`	Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
2010	J	`jnl`	Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. Very Large Scale Integr. Syst. Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2009	A*	`conf`	Multiple clock and voltage domains for chip multi processors. MICRO Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser
2009	—	`conf`	Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
2009	J	`jnl`	QNoC asynchronous router. Integr. Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny
2009	A*	`conf`	The Capacity Allocation Paradox. INFOCOM Asaf Baron, Ran Ginosar, Isaac Keslassy
2009	J	`jnl`	Two-phase synchronization with sub-cycle latency. Integr. Rostislav (Reuven) Dobkin, Ran Ginosar
2008	—	`conf`	Fast Universal Synchronizers. PATMOS Rostislav (Reuven) Dobkin, Ran Ginosar
2008	J	`jnl`	Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors. IEEE Trans. Very Large Scale Integr. Syst. A. Elyada, Ran Ginosar, Uri C. Weiser
2008	—	`conf`	Parallel vs. serial on-chip communication. SLIP Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar
2008	—	`conf`	Timing optimization in logic with interconnect. SLIP Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2007	—	`conf`	Access Regulation to Hot-Modules in Wormhole NoCs. NOCS Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2007	J	`jnl`	Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme. IEEE Trans. Neural Networks Rami Rom, Jacob Erel, Michael Glikson, Randy A. Lieberman, Kobi Rosenblum, Ofer Binah, Ran Ginosar, David L. Hayes
2007	J	`jnl`	An Integrated System for Multichannel Neuronal Recording With Spike/LFP Separation, Integrated A/D Conversion and Threshold Detection. IEEE Trans. Biomed. Eng. Yevgeny Perelman, Ran Ginosar
2007	—	`conf`	High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. ASYNC Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny
2007	J	`jnl`	Network Delays and Link Capacities in Application-Specific Wormhole NoCs. VLSI Design Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2007	—	`conf`	QNoC Asynchronous Router with Dynamic Virtual Channel Allocation. NOCS Rostislav (Reuven) Dobkin, Ran Ginosar, Israel Cidon
2007	A	`conf`	Routing table minimization for irregular mesh NoCs. DATE Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2007	—	`conf`	The Power of Priority: NoC Based Distributed Cache Coherency. NOCS Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2006	J	`jnl`	A low-power inverted ladder D/a converter. IEEE Trans. Circuits Syst. II Express Briefs Yevgeny Perelman, Ran Ginosar
2006	J	`jnl`	A predictive synchronizer for periodic clock domains. Formal Methods Syst. Des. Uri Frank, Tsachy Kapschitz, Ran Ginosar
2006	A	`conf`	Efficient link capacity and QoS design for network-on-chip. DATE Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2006	—	`conf`	Fast Asynchronous Shift Register for Bit-Serial Communication. ASYNC Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny
2006	J	`jnl`	High Rate Data Synchronization in GALS SoCs. IEEE Trans. Very Large Scale Integr. Syst. Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou
2006	J	`jnl`	Minimal Energy Asynchronous Dynamic Adders. IEEE Trans. Very Large Scale Integr. Syst. Ilya Obridko, Ran Ginosar
2005	—	`conf`	An Asynchronous Router for Multiple Service Levels Networks on Chip. ASYNC Rostislav (Reuven) Dobkin, Victoria Vishnyakov, Eyal Friedman, Ran Ginosar
2005	—	`conf`	Formal Verification of Synchronizers. CHARME Tsachy Kapschitz, Ran Ginosar
2005	—	`conf`	Low energy asynchronous architectures. ISCAS (5) Ilya Obridko, Ran Ginosar
2005	—	`conf`	Low-leakage repeaters for NoC interconnects. ISCAS (1) Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2005	J	`jnl`	Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar
2004	—	`conf`	A Predictive Synchronizer for Periodic Clock Domains. PATMOS Uri Frank, Ran Ginosar
2004	A	`conf`	Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. DATE Alex Branover, Rakefet Kol, Ran Ginosar
2004	J	`jnl`	Asynchronous gate-diffusion-input (GDI) circuits. IEEE Trans. Very Large Scale Integr. Syst. Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar
2004	—	`conf`	Automatic hardware-efficient SoC integration by QoS network on chip. ICECS Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2004	—	`conf`	Comparative analysis of serial vs parallel links in NoC. SoC Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar
2004	J	`jnl`	Cost considerations in network on chip. Integr. Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2004	—	`conf`	Data Synchronization Issues in GALS SoCs. ASYNC Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou
2004	—	`conf`	Low energy asynchronous adders. ICECS Ilya Obridko, Ran Ginosar
2004	—	`conf`	Micro-modem - reliability solution for NoC communications. ICECS Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar
2004	J	`jnl`	QNoC: QoS architecture and design process for network on chip. J. Syst. Archit. Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny
2003	J	`jnl`	A clock-tuning circuit for system-on-chip. IEEE Trans. Very Large Scale Integr. Syst. Y. Elboim, Avinoam Kolodny, Ran Ginosar
2003	—	`conf`	Fourteen Ways to Fool Your Synchronizer. ASYNC Ran Ginosar
2003	J	`jnl`	Relative timing [asynchronous design]. IEEE Trans. Very Large Scale Integr. Syst. Ken S. Stevens, Ran Ginosar, Shai Rotem
2003	—	`conf`	Timing Measurements of Synchronization Circuits. ASYNC Yaron Semiat, Ran Ginosar
2002	B	`conf`	Parallel VLSI architecture for MAP turbo decoder. PIMRC Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar
2001	J	`jnl`	A low-light-level sensor for medical diagnostic applications. IEEE J. Solid State Circuits Yevgeny Perelman, Ran Ginosar
2001	J	`jnl`	An asynchronous instruction length decoder. IEEE J. Solid State Circuits Kenneth S. Stevens, Shai Rotem, Ran Ginosar, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun, Rakefet Kol, Charles Dike, Marly Roncken
1999	A*	`conf`	CAD Directions for High Performance Asynchronous Circuits. DAC Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, Marly Roncken
1999	—	`conf`	RAPPID: An Asynchronous Instruction Length Decoder. ASYNC Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun
1999	—	`conf`	Relative Timing. ASYNC Ken S. Stevens, Shai Rotem, Ran Ginosar
1998	A	`conf`	A low power video processor. ISLPED Uzi Zangi, Ran Ginosar
1998	C	`conf`	Adaptive synchronization. ICCD Ran Ginosar, Rakefet Kol
1998	—	`conf`	Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun
1998	J	`jnl`	Spatio-Chromatic Image Enhancement Based on a Model of Human Visual Information Processing. J. Vis. Commun. Image Represent. Stuart G. Wolf, Ran Ginosar, Yehoshua Y. Zeevi
1997	C	`conf`	A Double-Latched Asynchronous Pipeline. ICCD Rakefet Kol, Ran Ginosar
1996	—	`conf`	Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems. ASYNC Rakefet Kol, Ran Ginosar, Goel Samuel
1995	J	`jnl`	Self-timed is self-checking. J. Electron. Test. Ilana David, Ran Ginosar, Michael Yoeli
1994	—	`conf`	Adaptive sensitivity CCD image sensor. ICPR (3) Sarit Chen, Ran Ginosar
1994	—	`conf`	Spatio-chromatic model for colour image processing. ICPR (1) Stuart G. Wolf, Ran Ginosar, Yehoshua Y. Zeevi
1993	J	`jnl`	Control unit synthesis from a high-level language. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alan Rotman, Ran Ginosar
1993	—	`conf`	Self-Timed Architecture of a Reduced Instruction Set Computer. Asynchronous Design Methodologies Ilana David, Ran Ginosar, Michael Yoeli
1992	J	`jnl`	An Efficient Implementation of Boolean Functions as Self-Timed Circuits. IEEE Trans. Computers Ilana David, Ran Ginosar, Michael Yoeli
1992	J	`jnl`	Implementing Sequential Machines as Self-Timed Circuits. IEEE Trans. Computers Ilana David, Ran Ginosar, Michael Yoeli
1991	B	`conf`	CARMEL-4: The Unify-Spawn Machine for FCP. ICLP Arie Harsat, Ran Ginosar
1990	B	`conf`	An Extended RISC Methodology and its Application to FCP. ICLP Arie Harsat, Ran Ginosar
1990	J	`jnl`	CARMEL-2: A second generation VLSI architecture for Flat Concurrent Prolog. New Gener. Comput. Arie Harsat, Ran Ginosar
1990	C	`conf`	Foveating vision systems architecture: image acquisition and display. VCIP Yehoshua Y. Zeevi, Ran Ginosar
1990	J	`jnl`	On the potential of asynchronous pipelined processors. SIGARCH Comput. Archit. News Ran Ginosar, Nick Michell
1989	J	`jnl`	An efficient implementation of Boolean functions nd finite state machine as self-timed circuit. SIGARCH Comput. Archit. News Llana David, Ran Ginosar, Michael Yoeli
1989	J	`jnl`	Topological comparison of perfect shuffle and hypercube. Int. J. Parallel Program. Ran Ginosar, David Egozi
1988	—	`conf`	CARMEL-2: A Second Generation VLSI Architecture for Flat Concurrent Prolog. FGCS Arie Harsat, Ran Ginosar
1985	B	`conf`	Design and Implementation of Switching Systems for Parallel Processors. ICPP Ran Ginosar, Dwight D. Hill
1983	—	`conf`	Performance evaluation of the MP/C. AFIPS National Computer Conference Bruce W. Arden, Ran Ginosar
1982	J	`jnl`	MP/C: A Multiprocessor/Computer Architecture. IEEE Trans. Computers Bruce W. Arden, Ran Ginosar
1981	A*	`conf`	A Single-Relation Module for a Data Base Machine. ISCA Bruce W. Arden, Ran Ginosar
1981	A*	`conf`	MP/C: A Multiprocessor/Computer Architecture. ISCA Bruce W. Arden, Ran Ginosar