Ramón Ruiz Merino

24 papers A 1B 2C 4Journal 6Unranked 11
YearRankTypeTitle / Venue / Authors
2026 J jnl
An Efficient-Energy Charge-Domain Convolution Operator for CNN.
IEEE Access
José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Francisco Javier Andreo-Oliver
2025 C conf
Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs.
ISCAS
Ginés Doménech-Asensi, Francisco Javier Andreo-Oliver, Ramón Ruiz Merino, José Ángel Díaz-Madrid
2024 J jnl
A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors.
J. Real Time Image Process.
José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez
2023 C conf
A 12T SRAM in-Memory Computing differential current architecture for CNN implementations.
ISCAS
Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Ángel Díaz-Madrid
2021 J jnl
Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC.
Circuits Syst. Signal Process.
José Ángel Díaz-Madrid, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, Ramón Ruiz Merino
2020 J jnl
All-hardware SIFT implementation for real-time VGA images feature extraction.
J. Real Time Image Process.
Ginés Doménech-Asensi, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Víctor Manuel Brea Sánchez, Paula López
2020 C conf
Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations.
ISCAS
José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Javier Martínez
2018 J jnl
An all-hardware implementation of the subpixel refinement stage in SIFT algorithm.
Int. J. Circuit Theory Appl.
Pablo Rubio-Ibáñez, Ramón Ruiz Merino, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, José Ángel Díaz-Madrid, José-Alejandro López Alcantud
2018 — conf
Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision.
ICDSC
Ricardo Carmona-Galán, Jorge Fernández-Berni, Ángel Rodríguez-Vázquez, Paula López Martinez, Víctor Manuel Brea Sánchez, Diego Cabello Ferrer, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez
2013 J jnl
Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels.
Int. J. Circuit Theory Appl.
Ginés Doménech-Asensi, José Ángel Díaz-Madrid, Ramón Ruiz Merino
2012 — conf
A fourth order CMOS band pass filter for PIR sensors.
ICECS
Ginés Doménech-Asensi, F. Martinez-Viviente, J. Illade-Quinteiro, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, Juan Martínez-Alajarín, Francisco J. Fernández-Luque, Juan M. Carrillo, Miguel Angel Domínguez
2009 — conf
Personal Notes about the Figure and Legate of Professor Mira.
IWINAC (1)
Ramón Ruiz Merino
2009 A conf
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing.
DATE
José Ángel Díaz-Madrid, Harald Neubauer, Hans Hauer, Ginés Doménech-Asensi, Ramón Ruiz Merino
2008 C conf
Accurate and reusable macromodeling technique using a fuzzy-logic approach.
ISCAS
Ginés Doménech-Asensi, Juan Hinojosa, Ramón Ruiz Merino, José Ángel Díaz-Madrid
2007 — conf
Classification and Diagnosis of Heart Sounds and Murmurs Using Artificial Neural Networks.
IWINAC (1)
Juan Martínez-Alajarín, José López-Candel, Ramón Ruiz Merino
2007 B conf
Compression system for the phonocardiographic signal.
FPL
F. Javier Toledo-Moreo, A. Legaz-Cano, J. Javier Martínez-Álvarez, Juan Martínez-Alajarín, Ramón Ruiz Merino
2007 — conf
Optimization of the Compression Parameters of a Phonocardiographic Telediagnosis System Using Genetic Algorithms.
IWINAC (1)
Juan Martínez-Alajarín, F. Javier Garrigós-Guerrero, Ramón Ruiz Merino
2006 — conf
Detection of anomalous events in biomedical signals by wigner analysis and instant-wise Rényi entropy.
EUSIPCO
Salvador Gabarda, Gabriel Cristóbal, Juan Martínez-Alajarín, Ramón Ruiz Merino
2006 B conf
Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem.
FPL
Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López Alcantud
2005 — conf
Description and Simulation of Bio-inspired Systems Using VHDL-AMS.
IWINAC (2)
Ginés Doménech-Asensi, José-Alejandro López Alcantud, Ramón Ruiz Merino
2003 — conf
An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks.
IWANN (2)
José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Hans Hauer, Ramón Ruiz Merino
2003 — conf
Current Mode CMOS Synthesis of a Motor-Control Neural System.
IWANN (2)
Ginés Doménech-Asensi, Ramón Ruiz Merino, Hans Hauer, José Ángel Díaz-Madrid
2001 — conf
Automatic Recognition of Weld Regions in Radiographic Images of Welded Joints.
VIIP
Rafael Vilar, Juan Zapata-Pérez, Luis Bernabé, Ramón Ruiz Merino
1999 — conf
Implementing a fuzzy processor on programmable logic circuits: modularization criteria.
EUSFLAT-ESTYLF Joint Conf.
Esperanza M. López, Alfonso Aniorte Carbonell, Ramón Ruiz Merino