Ramiro Taco - RankMe

30 papers C 11Journal 8Unranked 11

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Assessment of 2T2R Logic-in-Memory in a Cycle-to-Cycle Variation-Aware Simulation Environment. NewCAS Martín Gavilánez, Silvana Guitarra, Ramiro Taco
2025	C	`conf`	Low Matchline Voltage Swing Content-Addressable Memory Cell. ISCAS Cristhopher Mosquera, Ramiro Taco, Benjamin Zambrano, Luis-Miguel Procel, Esteban Garzón, Marco Lanuzza
2025	C	`conf`	Non-Volatile Content-Addressable Memory For Energy-Efficient & High-Performance Search And Update Operations. ISCAS Alessandro Bedoya, Benjamin Zambrano, Ramiro Taco, Luis-Miguel Prócel, Marco Lanuzza, Esteban Garzón
2025	C	`conf`	Towards Low-Power High-Performance Content-Addressable Memory: A Robust Precharge-Free Approach. ISCAS Ramiro Taco, Esteban Garzón, Adam Teman, Leonid Yavits, Marco Lanuzza
2024	J	`jnl`	Designing Precharge-Free Energy-Efficient Content-Addressable Memories. IEEE Trans. Very Large Scale Integr. Syst. Ramiro Taco, Esteban Garzón, Robert Hanhan, Adam Teman, Leonid Yavits, Marco Lanuzza
2024	—	`conf`	Low Power, Energy Efficient and High Performance Triple Mode Logic for IoT Applications. PRIME Netanel Shavit, Inbal Stanger, Ramiro Taco, Leonid Yavits, Alexander Fish
2023	—	`conf`	Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. LASCAS Santiago S. Pérez, Alessandro Bedoya, Luis-Miguel Prócel, Ramiro Taco
2023	J	`jnl`	Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow. IEEE Access Netanel Shavit, Inbal Stanger, Ramiro Taco, Alexander Fish, Itamar Levi
2023	J	`jnl`	XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs. IEEE Trans. Circuits Syst. II Express Briefs Ariana Musello, Esteban Garzón, Marco Lanuzza, Luis-Miguel Prócel, Ramiro Taco
2022	J	`jnl`	A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic. IEEE J. Solid State Circuits Yizhak Shifman, Inbal Stanger, Netanel Shavit, Ramiro Taco, Alexander Fish, Joseph Shor
2022	—	`conf`	DMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems. LASCAS Kevin Vicuña, Luis-Miguel Prócel, Lionel Trojman, Ramiro Taco
2022	—	`conf`	Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells. LASCAS Ariana Musello, Santiago S. Pérez, Marco Villegas, Luis-Miguel Prócel, Ramiro Taco, Lionel Trojman
2022	—	`conf`	Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. LASCAS Esteban Garzón, Ramiro Taco, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza
2021	—	`conf`	High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. LASCAS Ricardo Escobar, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza, Ramiro Taco
2021	C	`conf`	Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. ISCAS Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish
2021	C	`conf`	Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET. ISCAS Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish
2021	—	`conf`	RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies. LASCAS Lionel Trojman, David Rivadeneira, Marco Villegas, Eliana Acurio, Marco Lanuzza, Luis-Miguel Procel, Ramiro Taco
2020	C	`conf`	Dual Mode Logic Address Decoder. ISCAS Leonid Yavits, Ramiro Taco, Netanel Shavit, Inbal Stanger, Alexander Fish
2020	C	`conf`	Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology. ISCAS Ramiro Taco, Leonid Yavits, Netanel Shavit, Inbal Stanger, Marco Lanuzza, Alexander Fish
2020	—	`conf`	Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications. LASCAS Esteban Garzón, Benjamin Zambrano, Tatiana Moposita, Ramiro Taco, Luis-Miguel Prócel, Lionel Trojman
2020	C	`conf`	Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance. ISCAS Inbal Stanger, Netanel Shavit, Ramiro Taco, Leonid Yavits, Marco Lanuzza, Alexander Fish
2020	J	`jnl`	Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. IEEE Trans. Circuits Syst. II Express Briefs Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish
2019	J	`jnl`	An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI. IEEE J. Solid State Circuits Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
2019	C	`conf`	Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI. ISCAS Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
2017	C	`conf`	Evaluation of Dual Mode Logic in 28nm FD-SOI technology. ISCAS Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
2016	C	`conf`	Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology. ISCAS Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
2015	J	`jnl`	Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. Int. J. Circuit Theory Appl. Domenico Albano, Marco Lanuzza, Ramiro Taco, Felice Crupi
2015	J	`jnl`	Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits. VLSI Design Ramiro Taco, Marco Lanuzza, Domenico Albano
2014	—	`conf`	Dynamic gate-level body biasing for subthreshold digital design. LASCAS Marco Lanuzza, Ramiro Taco, Domenico Albano
2014	—	`conf`	Improving speed and power characteristics of pulse-triggered flip-flops. LASCAS Marco Lanuzza, Ramiro Taco