Raminder Singh Bajwa

17 papers A* 1A 2C 2Misc 3Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2001 J jnl
Architecture-level power estimation and design experiments.
ACM Trans. Design Autom. Electr. Syst.
Rita Yu Chen, Mary Jane Irwin, Raminder Singh Bajwa
1998 A conf
A unified approach in the analysis of latches and flip-flops for low-power systems.
ISLPED
Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa
1998 C conf
Comparative analysis of latches and flip-flops for high-performance systems.
ICCD
Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa
1998 A* conf
Validation of an Architectural Level Power Analysis Technique.
DAC
Rita Yu Chen, Robert Michael Owens, Mary Jane Irwin, Raminder Singh Bajwa
1997 J jnl
Instruction buffering to reduce power in processors for signal processing.
IEEE Trans. Very Large Scale Integr. Syst.
Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki
1997 Misc conf
Mixed-autonomy local interconnect for reconfigurable SIMD arrays.
HiPC
Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
1996 Misc conf
Simultaneous speech segmentation and phoneme recognition using dynamic programming.
ICASSP
Raminder Singh Bajwa, Robert Michael Owens, Thomas P. Kelliher
1996 A conf
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer.
ISLPED
Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki
1995 C conf
Reducing the number of counters needed for integer multiplication.
IEEE Symposium on Computer Arithmetic
Robert Michael Owens, Raminder Singh Bajwa, Mary Jane Irwin
1995 — conf
The MGAP's programming environment and the *C++ language.
ASAP
Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
1994 — conf
A SIMD solution to the sequence comparison problem on the MGAP.
ASAP
Manjit Borah, Raminder Singh Bajwa, Sridhar Hannenhalli, Mary Jane Irwin
1994 J jnl
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.
IEEE Trans. Computers
Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
1994 — conf
Rapid prototyping with programmable control paths.
ASAP
Raminder Singh Bajwa, Chetana N. Keltcher, Paul Keltcher, Mary Jane Irwin
1993 Misc conf
A Massively Parallel, Micro-Grained VLSI Architecture.
VLSI Design
Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
1993 — conf
Image Processing with the MGAP: A Cost Effective Solution.
IPPS
Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
1993 J jnl
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system.
IEEE Trans. Very Large Scale Integr. Syst.
Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, Wen-Lin Yang
1992 — conf
Implementing a family of high performance, micrograined architectures.
ASAP
Robert Michael Owens, Mary Jane Irwin, Thomas P. Kelliher, Mohan Vishwanath, Raminder Singh Bajwa