Ramesh Vaddi

37 papers A 2C 3Misc 1Journal 19Unranked 12
YearRankTypeTitle / Venue / Authors
2025 J jnl
FeSATLock: An Energy Efficient and SAT Attack Resilient Logic Locking Design With FeFET LUT Architecture for Enhanced Hardware Security.
IEEE Access
Tirumalarao Kadiyam, Venu Birudu, Aditya Japa, Fadi N. Sibai, Venkateswarlu Gonuguntla, Ramesh Vaddi
2025 J jnl
TRSBi-YOLO: Transformer based lightweight and high-performance model for PCB defects detection.
J. Supercomput.
Vinod Kumar Ancha, Venkateswarlu Gonuguntla, Ramesh Vaddi
2024 C conf
Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices.
ISCAS
Venu Birudu, Tirumalarao Kadiyam, Koteswararao Penumalli, Aditya Japa, Sushma Nirmala Sambatur, Chongyan Gu, Siva Sankar Yellampalli, Ramesh Vaddi
2024 J jnl
Utilizing YOLO Models for Real-World Scenarios: Assessing Novel Mixed Defect Detection Dataset in PCBs.
IEEE Access
Vinod Kumar Ancha, Fadi N. Sibai, Venkateswarlu Gonuguntla, Ramesh Vaddi
2023 J jnl
A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks.
Microelectron. J.
Venu Birudu, Siva Sankar Yellampalli, Ramesh Vaddi
2023 J jnl
Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design.
Microelectron. J.
Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi
2022 J jnl
Chest X ray and cough sample based deep learning framework for accurate diagnosis of COVID-19.
Comput. Electr. Eng.
Santosh Kumar, Rishab Nagar, Saumya Bhatnagar, Ramesh Vaddi, Sachin Kumar Gupta, Mamoon Rashid, Ali Kashif Bashir, Tamim Alkhalifah
2022 — conf
Design and Exploration of Negative Capacitance FETs for Energy Efficient SRAM based In-Memory XNOR/Input and Weight Product Operation for Deep Neural Networks.
iSES
Venu Birudu, Siva Sankar Yellampalli, Ramesh Vaddi
2022 J jnl
Negative capacitance FETs for energy efficient and hardware secure logic designs.
Microelectron. J.
Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi
2021 — conf
Design and Analysis of 4-bit and 5-bit Flash ADC's in 90nm CMOS Technology for Energy Efficient IoT Applications.
iSES
Varanasi Koundinya, Madanu Karun Chand, Dharmavarapu Dhushyanth, Devarajugattu Jayanth Saikumar, Arumalla Varun Sai, Venu Birudu, Ramesh Vaddi
2021 — conf
Steep Switching NCFET based Logic for Future Energy Efficient Electronics.
iSES
Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi
2021 — conf
Systolic Array based Multiply Accumulation Unit for IoT Edge Accelerators.
iSES
P. L. Lahari, Siva Sankar Yellampalli, Ramesh Vaddi
2021 J jnl
Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things.
Int. J. Circuit Theory Appl.
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2020 C conf
A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET.
ISCAS
Aditya Japa, Yellappa Palagani, Venkateswarlu Gonuguntla, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Jun Rim Choi, Ramesh Vaddi
2020 J jnl
Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator.
IET Circuits Devices Syst.
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2020 J jnl
Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage.
Int. J. Circuit Theory Appl.
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2019 A conf
Multi-objective Precision Optimization of Deep Neural Networks for Edge Devices.
DATE
Nhut-Minh Ho, Ramesh Vaddi, Weng-Fai Wong
2019 J jnl
Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks.
IET Circuits Devices Syst.
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2018 — conf
A Low-power Low-noise Open-loop Configured Signal Folding Neural Recording Amplifier.
ISOCC
Gauri Punekar, Venkateswarlu Gonuguntla, Yellappa Palagani, Jun Rim Choi, Ramesh Vaddi
2018 J jnl
Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD.
J. Circuits Syst. Comput.
Sadulla Shaik, Kalva Sri Rama Krishna, Ramesh Vaddi
2018 C conf
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities.
ISCAS
Aditya Japa, T. Nagateja, Santosh Kumar Vishvakarma, Yellappa Palagani, Jun Rim Choi, Ramesh Vaddi
2017 — conf
A low voltage capacitor based current controlled sense amplifier for input offset compensation.
ISOCC
Y. Sudha Vani, N. Usha Rani, Ramesh Vaddi
2017 — conf
Energy efficient and high throughput transceiver design in the capacitive coupling mode exploring tunnel transistors for 3D ICs.
ISOCC
T. Nagateja, Ramesh Vaddi
2017 — conf
Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs.
VDAT
Aditya Japa, Harshita Vallabhaneni, Ramesh Vaddi
2017 — conf
Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics.
VDAT
Y. Sudha Vani, N. Usha Rani, Ramesh Vaddi
2017 — conf
Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms.
iNIS
Aditya Japa, T. Nagateja, Ramesh Vaddi
2016 Misc conf
Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing.
VLSID
Sadulla Shaik, Kalva Sri Rama Krishna, Ramesh Vaddi
2016 J jnl
Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction.
IET Circuits Devices Syst.
Aditya Japa, Harshita Vallabhaneni, Ramesh Vaddi
2014 J jnl
Tunnel FET RF Rectifier Design for Energy Harvesting Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Huichu Liu, Xueqing Li, Ramesh Vaddi, Kaisheng Ma, Suman Datta, Vijaykrishnan Narayanan
2014 — conf
Tunnel FET based low voltage static vs dynamic logic families for energy efficiency.
VDAT
Kasturi Subramanyam, Sadulla Shaik, Ramesh Vaddi
2013 A conf
Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier.
ISLPED
Huichu Liu, Ramesh Vaddi, Suman Datta, Vijaykrishnan Narayanan
2011 J jnl
Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options.
Microelectron. J.
Ramesh Vaddi, R. P. Agarwal, Sudeb Dasgupta
2011 — conf
Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET.
ISVLSI
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
2010 J jnl
Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic.
IET Circuits Devices Syst.
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
2010 J jnl
Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs.
J. Low Power Electron.
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
2010 J jnl
Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic.
Microelectron. J.
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal
2009 J jnl
Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications.
VLSI Design
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal